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GRAPHICS DIGITIZER. TVP7000 Datasheet

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GRAPHICS DIGITIZER. TVP7000 Datasheet






TVP7000 DIGITIZER. Datasheet pdf. Equivalent




TVP7000 DIGITIZER. Datasheet pdf. Equivalent





Part

TVP7000

Description

VIDEO AND GRAPHICS DIGITIZER



Feature


TVP7000 www.ti.com TRIPLE 8/10-BIT, 15 0/110 MSPS, VIDEO AND GRAPHICS DIGITIZE R WITH ANALOG PLL SLES143 – SEPTEMBE R 2005 FEATURES β€’ Analog Channels β€ “ -6 dB to 6 dB Analog Gain – Analog Input MUXs – Auto Video Clamp – Thr ee Digitizing Channels, Each With Indep endently Controllable Clamp, PGA, and A DC – Clamping: Selectable Clamping Be tween Bottom Level and Mid-level.
Manufacture

Texas Instruments

Datasheet
Download TVP7000 Datasheet


Texas Instruments TVP7000

TVP7000; – Offset: 1024-Step Programmable RGB or YPbPr Offset Control – PGA: 8-Bit Programmable Gain Amplifier – ADC: 8/ 10-Bit 150/110 MSPS A/D Converter – A utomatic Level Control Circuit – Comp osite Sync: Integrated Sync-on-Green Ex traction From GreenLuminance Channel β€ “ Support for DC and AC-Coupled Input S ignals β€’ PLL – Fully Integrated Ana log PLL for Pixel Clock Generation.


Texas Instruments TVP7000

– 12-150 MHz Pixel Clock Generation F rom HSYNC Input – Adjustable PLL Loop Bandwidth for Minimum Jitter – 5-Bit Programmable Subpixel Accurate Positio ning of Sampling Phase β€’ Output Forma tter – Support for RGB/YCbCr 4:4:4 an d YCbCr 4:2:2 Output Modes to Reduce Bo ard Traces – Dedicated DATACLK Output for Easy Latching of Output Data β€’ S ystem – Industry-Standard Normal.


Texas Instruments TVP7000

/Fast I2C Interface With Register Readba ck Capability – Space-Saving TQFP-100 Pin Package – Thermally-Enhanced Pow erPADβ„’ Package for Better Heat Dissip ation APPLICATIONS β€’ LCD TV/Monitors /Projectors β€’ DLP TV/Projectors β€’ P DP TV/Monitors β€’ PCTV Set-Top Boxes β €’ Digital Image Processing β€’ Video C apture/Video Editing β€’ Scan Rate/Imag e Resolution Converters β€’ Video Confer.

Part

TVP7000

Description

VIDEO AND GRAPHICS DIGITIZER



Feature


TVP7000 www.ti.com TRIPLE 8/10-BIT, 15 0/110 MSPS, VIDEO AND GRAPHICS DIGITIZE R WITH ANALOG PLL SLES143 – SEPTEMBE R 2005 FEATURES β€’ Analog Channels β€ “ -6 dB to 6 dB Analog Gain – Analog Input MUXs – Auto Video Clamp – Thr ee Digitizing Channels, Each With Indep endently Controllable Clamp, PGA, and A DC – Clamping: Selectable Clamping Be tween Bottom Level and Mid-level.
Manufacture

Texas Instruments

Datasheet
Download TVP7000 Datasheet




 TVP7000
TVP7000
www.ti.com
TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO
AND GRAPHICS DIGITIZER WITH ANALOG PLL
SLES143 – SEPTEMBER 2005
FEATURES
β€’ Analog Channels
– -6 dB to 6 dB Analog Gain
– Analog Input MUXs
– Auto Video Clamp
– Three Digitizing Channels, Each With
Independently Controllable Clamp, PGA,
and ADC
– Clamping: Selectable Clamping Between
Bottom Level and Mid-level
– Offset: 1024-Step Programmable RGB or
YPbPr Offset Control
– PGA: 8-Bit Programmable Gain Amplifier
– ADC: 8/10-Bit 150/110 MSPS A/D Converter
– Automatic Level Control Circuit
– Composite Sync: Integrated Sync-on-Green
Extraction From GreenLuminance Channel
– Support for DC and AC-Coupled Input
Signals
β€’ PLL
– Fully Integrated Analog PLL for Pixel Clock
Generation
– 12-150 MHz Pixel Clock Generation From
HSYNC Input
– Adjustable PLL Loop Bandwidth for
Minimum Jitter
– 5-Bit Programmable Subpixel Accurate
Positioning of Sampling Phase
β€’ Output Formatter
– Support for RGB/YCbCr 4:4:4 and YCbCr
4:2:2 Output Modes to Reduce Board Traces
– Dedicated DATACLK Output for Easy
Latching of Output Data
β€’ System
– Industry-Standard Normal/Fast I2C Interface
With Register Readback Capability
– Space-Saving TQFP-100 Pin Package
– Thermally-Enhanced PowerPADβ„’ Package
for Better Heat Dissipation
APPLICATIONS
β€’ LCD TV/Monitors/Projectors
β€’ DLP TV/Projectors
β€’ PDP TV/Monitors
β€’ PCTV Set-Top Boxes
β€’ Digital Image Processing
β€’ Video Capture/Video Editing
β€’ Scan Rate/Image Resolution Converters
β€’ Video Conferencing
β€’ Video/Graphics Digitizing Equipment
DESCRIPTION
TVP7000 is a complete solution for digitizing video
and graphic signals in RGB or YPbPr color spaces.
The device supports pixel rates up to 150 MHz.
Therefore, it can be used for PC graphics digitizing
up to the VESA standard of SXGA (1280 Γ— 1024)
resolution at 75 Hz screen refresh rate, and in video
environments for the digitizing of digital TV formats,
including HDTV up to 1080p. TVP7000 can be used
to digitize CVBS and S-Video signal with 10-bit
ADCs.
The TVP7000 is powered from 3.3-V and 1.8-V
supply and integrates a triple high-performance A/D
converter with clamping functions and variable gain,
independently programmable for each channel. The
clamping timing window is provided by an external
pulse or can be generated internally. The TVP7000
includes analog slicing circuitry on the Y or G input to
support sync-on-luminance or sync-on-green extrac-
tion. In addition, TVP7000 can extract discrete
HSYNC and VSYNC from composite sync using a
sync slicer.
TVP7000 also contains a complete analog PLL block
to generate a pixel clock from the HSYNC input. Pixel
clock output frequencies range from 12 MHz to 150
MHz.
All programming of the part is done via an indus-
try-standard I2C interface, which supports both read-
ing and writing of register settings. The TVP7000 is
available in a space-saving TQFP 100-pin PowerPAD
package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright Β© 2005, Texas Instruments Incorporated




 TVP7000
TVP7000
SLES143 – SEPTEMBER 2005
RIN_1
RIN_2
RIN_3
GIN_1
GIN_2
GIN_3
GIN_4
BIN_1
BIN_2
BIN_3
www.ti.com
TA
0Β°C to 70Β°C
ORDERING INFORMATION
PACKAGED DEVICES
100-PIN PLASTIC FLATPACK PowerPADβ„’
TVP7000PZP
FUNCTIONAL BLOCK DIAGRAM
Clamp
PGA
Clamp
PGA
10βˆ’bit
ADC
10βˆ’bit
ADC
Output
Formatter
ROUT[9:0]
GOUT[9:0]
Clamp
PGA
10βˆ’bit
ADC
BOUT[9:0]
SOGIN_1
SOGIN_2
SOGIN_3
HSYNC_A
HSYNC_B
VSYNC_A
VSYNC_B
COAST
CLAMP
EXT_CLK
FILT1
FILT2
PWDN
RESETB
SCL
SDA
I2CA
Timing Processor
and Clock generation
Host
Interface
DATACLK
SOGOUT
HSOUT
VSOUT
2




 TVP7000
www.ti.com
TERMINAL ASSIGNMENTS
TVP7000
SLES143 – SEPTEMBER 2005
SOGIN_1
1
GIN_1
2
A18GND
3
A18VDD
4
A18GND
5
A18VDD
6
A18VDD
7
A18GND
8
RIN_3
9
RIN_2
10
RIN_1
11
A33GND
12
A33VDD
13
A33VDD
14
A33GND
15
BIN_3
16
BIN_2
17
BIN_1
18
A18VDD
19
A18GND
20
NSUB
21
TEST
22
VSOUT
23
HSOUT
24
SOGOUT
25
TVP7000
100βˆ’Pin TQFP Package
(Top View)
75
SDA
74
SCL
73
I2CA
72
TMS
71
RESETB
70
PWDN
69
DVDD
68
GND
67
IOGND
66
IOVDD
65
R_0
64
R_1
63
R_2
62
R_3
61
R_4
60
IOGND
59
R_5
58
R_6
57
R_7
56
R_8
55
R_9
54
IOGND
53
IOVDD
52
G_0
51
G_1
3



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