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Interface Circuit. MT9171 Datasheet

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Interface Circuit. MT9171 Datasheet






MT9171 Circuit. Datasheet pdf. Equivalent




MT9171 Circuit. Datasheet pdf. Equivalent





Part

MT9171

Description

Digital Network Interface Circuit



Feature


ISO2-CMOS ST-BUS FAMILY MT9171/72 Dig ital Subscriber Interface Circuit Digit al Network Interface Circuit Data Sheet Features • Full duplex transmission over a single twisted pair • Selecta ble 80 or 160 kbit/s line rate • Adap tive echo cancellation • Up to 3 km ( 9171) and 4 km (9172) • ISDN compatib le (2B+D) data format • Transparent m odem capability • Frame synchron.
Manufacture

Zarlink

Datasheet
Download MT9171 Datasheet


Zarlink MT9171

MT9171; ization and clock extraction • Zarlink ST-BUS compatible • Low power (typic ally 50 mW), single 5 V supply Applicat ions • Digital subscriber lines • H igh speed data transmission over twiste d wires • Digital PABX line cards and telephone sets • 80 or 160 kbit/s si ngle chip modem March 2006 Ordering I nformation MT9171/72AE MT9171/72AN MT9 171/72AP MT9171/72APR MT9171/7.


Zarlink MT9171

2ANR MT9171/72AE1 MT9171/72AP1 MT9171/72 AN1 MT9171/72APR1 MT9171/72ANR1 22 Pin PDIP 24 Pin SSOP 28 Pin PLCC 28 Pin PL CC 24 Pin SSOP 22 Pin PDIP* 28 Pin PLCC * 24 Pin SSOP* 28 Pin PLCC* 24 Pin SSOP * *Pb Free Matte Tin -40°C to +85°C Tubes Tubes Tubes Tape & Reel Tape & Reel Tubes Tubes Tubes Tape & Reel Tape & Reel Description The MT9171 (DSIC) and MT9172 (DNIC) ar.


Zarlink MT9171

e pin for pin compatible replacements fo r the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex d igital transmission up to 160 kbit/s ov er a twisted wire pair. They use adapti ve echo-cancelling techniques and trans fer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an.

Part

MT9171

Description

Digital Network Interface Circuit



Feature


ISO2-CMOS ST-BUS FAMILY MT9171/72 Dig ital Subscriber Interface Circuit Digit al Network Interface Circuit Data Sheet Features • Full duplex transmission over a single twisted pair • Selecta ble 80 or 160 kbit/s line rate • Adap tive echo cancellation • Up to 3 km ( 9171) and 4 km (9172) • ISDN compatib le (2B+D) data format • Transparent m odem capability • Frame synchron.
Manufacture

Zarlink

Datasheet
Download MT9171 Datasheet




 MT9171
ISO2-CMOS ST-BUSFAMILY MT9171/72
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
Data Sheet
Features
• Full duplex transmission over a single twisted pair
• Selectable 80 or 160 kbit/s line rate
• Adaptive echo cancellation
• Up to 3 km (9171) and 4 km (9172)
• ISDN compatible (2B+D) data format
• Transparent modem capability
• Frame synchronization and clock extraction
• Zarlink ST-BUS compatible
• Low power (typically 50 mW), single 5 V supply
Applications
• Digital subscriber lines
• High speed data transmission over twisted wires
• Digital PABX line cards and telephone sets
• 80 or 160 kbit/s single chip modem
March 2006
Ordering Information
MT9171/72AE
MT9171/72AN
MT9171/72AP
MT9171/72APR
MT9171/72ANR
MT9171/72AE1
MT9171/72AP1
MT9171/72AN1
MT9171/72APR1
MT9171/72ANR1
22 Pin PDIP
24 Pin SSOP
28 Pin PLCC
28 Pin PLCC
24 Pin SSOP
22 Pin PDIP*
28 Pin PLCC*
24 Pin SSOP*
28 Pin PLCC*
24 Pin SSOP*
*Pb Free Matte Tin
-40°C to +85°C
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Description
The MT9171 (DSIC) and MT9172 (DNIC) are pin for
pin compatible replacements for the MT8971 and
MT8972, respectively. They are multi-function devices
capable of providing high speed, full duplex digital
transmission up to 160 kbit/s over a twisted wire pair.
They use adaptive echo-cancelling techniques and
transfer data in (2B+D) format compatible to the ISDN
basic rate. Several modes of operation allow an easy
interface to digital telecommunication networks
including use as a high speed limited distance modem
DSTi/Di
CDSTi/
CDi
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
DSTo/Do
CDSTo/
CDo
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
Control
Register
Transmit
Timing
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control Sync Detect
DPLL
Status
Receive
Address
Echo Canceller
Error
Signal Echo Estimate
+
Receive
Filter
VBias
MUX
-1
+2
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
VDD VSS VBias VRef
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
LOUT
LOUT
DIS
Precan
LIN
OSC2
OSC1




 MT9171
MT9171/72
Data Sheet
with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop
reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted.
The MT9171/72 is fabricated in Zarlink’s ISO2-CMOS process.
LOUT 1
VBias 2
VRef 3
MS2 4
MS1 5
MS0 6
RegC 7
F0/CLD 8
CDSTi/CDi 9
CDSTo/CDo 10
VSS 11
22 VDD
21 LIN
20 TEST
19 LOUT DIS
18 Precan
17 OSC1
16 OSC2
15 C4/TCK
14 F0o/RCK
13 DSTi/Di
12 DSTo/Do
MS2 5
NC 6
MS1 7
MS0 8
RegC 9
F0/CLD 10
NC 11
25 NC
24 LOUT DIS
23 Precan
22 OSC1
21 OSC2
20 NC
19 C4/TCK
22 PIN PDIP
LOUT
VBias
VRef
MS2
MS1
MS0
RegC
NC
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
24 PIN SSOP
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
NC
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
22 24 28
Name
Description
11
22
33
4,5, 4,5,
66
77
2
LOUT Line Out. Transmit Signal output (Analog). Referenced to VBias.
3
VBias Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD.
4
VRef Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to
VDD.
5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the
8
various operating modes for a particular application. See Table 1 for the
operating modes.
9
RegC Regulator Control output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
8 9 10 F0/CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative
pulse input for the MASTER indicating the start of the active channel times of the
device. Output for the SLAVE indicating the start of the active channel times of
the device. Output in MOD mode providing a pulse indicating the start of the C-
channel.
2
Zarlink Semiconductor Inc.




 MT9171
MT9171/72
Data Sheet
Pin Description (continued)
Pin #
22 24 28
Name
Description
9 10
10 11
11 12
12 13
13 14
12 CDSTi/ Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control
CDi & signalling input in DN mode. In MOD mode this is a continuous bit stream at
the bit rate selected.
13 CDSTo/ Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial
CDo control & signalling output in DN mode. In MOD mode this is a continuous bit
stream at the bit rate selected.
14
VSS Negative Power Supply (0 V).
15 DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in
DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.
16 DSTi/Di Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
14 15
17 F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device
to allow daisy chaining. In MOD mode provides the receive bit rate clock to the
system.
15 16
16 17
17 19
18 20
8,
18
19 21
20 22
21 23
22 24
19 C4/TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible
clock input for the MASTER and output for the SLAVE in DN mode. For MOD
mode this pin provides the transmit bit rate clock to the system.
21 OSC2 Oscillator Output. CMOS Output.
22 OSC1 Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C.
Electrical Characteristics for OSC1 input requirements.
23 Precan Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the
precanceller is forced to VBias thus bypassing the precanceller section. When
logic ’0’, the LOUT to the precanceller path is enabled and functions normally. An
internal pulldown (50 k) is provided on this pin.
1,6,
NC No Connection. Leave open circuit
11,
18,
20,
25
24 LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When
logic “0”, LOUT functions normally. An internal pulldown (50 k) is provided on
this pin.
26 TEST Test Pin. Connect to VSS.
27
LIN Receive Signal input (Analog).
28
VDD Positive Power Supply (+5 V) input.
3
Zarlink Semiconductor Inc.






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