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CLOCK BUFFER. IDT2305 Datasheet

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CLOCK BUFFER. IDT2305 Datasheet
















IDT2305 BUFFER. Datasheet pdf. Equivalent













Part

IDT2305

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT2305 3.3V ZERO DELAY CLOCK BUFFER CO MMERCIAL AND INDUSTRIAL TEMPERATURE RAN GES 3.3V ZERO DELAY CLOCK BUFFER IDT2 305 FEATURES: • Phase-Lock Loop Cloc k Distribution • 10MHz to 133MHz oper ating frequency • Distributes one clo ck input to one bank of five outputs Zero Input-Output Delay • Output Sk ew < 250ps • Low jitter <200 ps cycle -to-cycle • IDT2305-1 for Stan.
Manufacture

Renesas

Datasheet
Download IDT2305 Datasheet


Renesas IDT2305

IDT2305; dard Drive • IDT2305-1H for High Drive • No external RC network required Operates at 3.3V VDD • Power down m ode • Available in SOIC/TSSOP package s DESCRIPTION: The IDT2305 is a high-s peed phase-lock loop (PLL) clock buffer , designed to address high-speed clock distribution applications. The zero del ay is achieved by aligning the phase be tween the incoming clock and.


Renesas IDT2305

the output clock, operable within the r ange of 10 to 133MHz. The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one reference input, and drives out five low skew clocks. The -1H vers ion of this device operates, up to 133M Hz frequency and has a higher drive tha n the -1 device. All parts have on-chip PLLs which lock to an input clock on t he REF pin. The PL.


Renesas IDT2305

L feedback is on-chip and is obtained fr om the CLKOUT pad. In the absence of an input clock, the IDT2305 enters power down. In this mode, the device will dra w less than 25µA, the outputs are tri- stated, and the PLL is not running, res ulting in a significant reduction of po wer. The IDT2305 is characterized for b oth Industrial and Commercial operation . FUNCTIONAL BLOCK.





Part

IDT2305

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT2305 3.3V ZERO DELAY CLOCK BUFFER CO MMERCIAL AND INDUSTRIAL TEMPERATURE RAN GES 3.3V ZERO DELAY CLOCK BUFFER IDT2 305 FEATURES: • Phase-Lock Loop Cloc k Distribution • 10MHz to 133MHz oper ating frequency • Distributes one clo ck input to one bank of five outputs Zero Input-Output Delay • Output Sk ew < 250ps • Low jitter <200 ps cycle -to-cycle • IDT2305-1 for Stan.
Manufacture

Renesas

Datasheet
Download IDT2305 Datasheet




 IDT2305
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK BUFFER
IDT2305
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2305-1 for Standard Drive
• IDT2305-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Available in SOIC/TSSOP packages
DESCRIPTION:
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
reference input, and drives out five low skew clocks. The -1H version of this
device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25µA, the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
1
REF
PLL
Control
Logic
8
CLKOUT
3
CLK1
2 CLK2
5 CLK3
7
CLK4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2012 Integrated Device Technology, Inc.
AUGUST 2012
DSC 5174/8




 IDT2305
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
PIN CONFIGURATION
REF
1
8
CLK2
2
7
CLK1
3
6
GND
4
5
SOIC/TSSOP
TOP VIEW
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
CLKOUT
CLK4
VDD
CLK3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max.
Unit
VDD
Supply Voltage Range
–0.5 to +4.6 V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5 V
VI
Input Voltage Range
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50
mA
IO (VO = 0 to VDD) ContinuousOutputCurrent
±50
mA
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG
Operating
Storage Temperature Range
Commercial Temperature
–65 to +150 °C
0 to +70 °C
Temperature
Range
Operating
Temperature
Industrial Temperature
Range
-40 to +85 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name
REF
CLK2(1)
CLK1(1)
GND
CLK3(1)
VDD
CLK4(1)
CLKOUT(1)
Pin Number
1
2
3
4
5
6
7
8
NOTES:
1. Weak pull down on all outputs.
Type
IN
Out
Out
Ground
Out
PWR
Out
Out
Functional Description
Input reference clock, 5 Volt tolerant input
Output clock
Output clock
Ground
Output clock
3.3V Supply
Output clock
Output clock, internal feedback on this pin
2




 IDT2305
IDT2305
3.3V ZERO DELAY CLOCK BUFFER
OPERATING CONDITIONS - COMMERCIAL
Symbol
Parameter
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance < 100MHz
Load Capacitance 100MHz - 133MHz
CIN
Input Capacitance
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Min.
Max.
Unit
3
3.6
V
0
70
°C
30
pF
10
7
pF
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
VIL
Input LOW Voltage Level
VIH
Input HIGH Voltage Level
IIL
Input LOW Current
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
VOL
Output LOW Voltage
Standard Drive
IOL = 8mA
High Drive
IOL = 12mA (-1H)
VOH
Output HIGH Voltage
Standard Drive
IOH = -8mA
High Drive
IOH = -12mA (-1H)
IDD_PD
Power Down Current
REF = 0MHz
IDD
Supply Current
Unloaded Outputs at 66.66MHz
Min.
Max.
Unit
0.8
V
2
V
50
µA
100
µA
0.4
V
2.4
V
12
µA
32
mA
(1,2)
SWITCHING CHARACTERISTICS (2305-1) - COMMERCIAL
Symbol
Parameter
Conditions
Min.
t1
Output Frequency
10pF Load
10
30pF Load
10
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
t3
Rise Time
Measured between 0.8V and 2V
t4
Fall Time
Measured between 0.8V and 2V
t5
Output to Output Skew
All outputs equally loaded
t6
Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
tJ
Cycle-to-Cycle Jitter, pk - pk
Measured at 66.66MHz, loaded outputs
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin —
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
Typ. Max. Unit
— 133 MHz
— 100
50 60
%
— 2.5
ns
— 2.5
ns
— 250
ps
0 ±350 ps
0 700
ps
— 200
ps
1
ms
3




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