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CLOCK BUFFER. IDT2308 Datasheet

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CLOCK BUFFER. IDT2308 Datasheet
















IDT2308 BUFFER. Datasheet pdf. Equivalent













Part

IDT2308

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK MULTIPLI ER IDT2308 FEATURES: • Phase-Lock L oop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock in put to two banks of four outputs • Se parate output enable for each output ba nk • External feedback (.
Manufacture

Renesas

Datasheet
Download IDT2308 Datasheet


Renesas IDT2308

IDT2308; FBK) pin is used to synchronize the outp uts to the clock input • Output Skew <200 ps • Low jitter <200 ps cycle-to -cycle • 1x, 2x, 4x output options (s ee table): – IDT2308-1 1x – IDT2308 -2 1x, 2x – IDT2308-3 2x, 4x – IDT2 308-4 2x – IDT2308-1H, -2H, and -5H f or High Drive • No external RC networ k required • Operates at 3.3V VDD • Available in SOIC and TSSOP packages D.


Renesas IDT2308

ESCRIPTION: The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed c lock distribution and multiplication ap plications. The zero delay is achieved by aligning the phase between the incom ing clock and the output clock, operabl e within the range of 10 to 133MHz. The IDT2308 has two banks of four outputs each that are cont.


Renesas IDT2308

rolled via two select addresses. By prop er selection of input addresses, both b anks can be put in tri-state mode. In t est mode, the PLL is turned off, and th e input clock directly drives the outpu ts for system testing purposes. In the absence of an input clock, the IDT2308 enters power down, and the outputs are tri-stated. In this mode, the device wi ll draw less than .





Part

IDT2308

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK MULTIPLI ER IDT2308 FEATURES: • Phase-Lock L oop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock in put to two banks of four outputs • Se parate output enable for each output ba nk • External feedback (.
Manufacture

Renesas

Datasheet
Download IDT2308 Datasheet




 IDT2308
IDT2308
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK MULTIPLIER
IDT2308
FEATURES:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT2308-1 1x
– IDT2308-2 1x, 2x
– IDT2308-3 2x, 4x
– IDT2308-4 2x
– IDT2308-1H, -2H, and -5H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
DESCRIPTION:
The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308 has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT2308 enters power down, and the outputs are tri-stated. In
this mode, the device will draw less than 25μA.
The IDT2308 is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT2308 is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
16
FBK
2
1
PLL
REF
2
(-5)
S2 8
S1 9
Control
Logic
(-2, -3) 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2016 Integrated Device Technology, Inc.
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
OCTOBER 2016
DSC 5173/12




 IDT2308
IDT2308
3.3V ZERO DELAY CLOCK MULTIPLIER
PIN CONFIGURATION
REF
1
CLKA1
2
CLKA2
3
VDD
4
GND
5
CLKB1
6
CLKB2
7
S2
8
16 FBK
15
CLKA4
14
CLKA3
13
VDD
12
GND
11 CLKB4
10
CLKB3
9
S1
SOIC/ TSSOP
TOP VIEW
PIN DESCRIPTION
REF
CLKA1(1)
CLKA2(1)
VDD
GND
CLKB1(1)
CLKB2(1)
S2(2)
S1(2)
CLKB3(1)
CLKB4(1)
GND
VDD
CLKA3(1)
CLKA4(1)
FBK
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Functional Description
Input Reference Clock, 5 Volt Tolerant Input
Clock Output for Bank A
Clock Output for Bank A
3.3V Supply
Ground
Clock Output for Bank B
Clock Output for Bank B
Select Input, Bit 2
Select Input, Bit 1
Clock Output for Bank B
Clock Output for Bank B
Ground
3.3V Supply
Clock Output for Bank A
Clock Output for Bank A
PLL Feedback Input
NOTES:
1. Weak pull down on all outputs.
2. Weak pull ups on these inputs.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max.
Unit
VDD
Supply Voltage Range
–0.5 to +4.6 V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5 V
VI
Input Voltage Range
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50
mA
IOK
Terminal Voltage with Respect
±50
mA
(VO < 0 or VO > VDD) to GND (inputs VIH 2.5, VIL 2.5)
IO
Continuous Output Current
±50
mA
(VO = 0 to VDD)
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG
StorageTemperatureRange –65 to +150 °C
Operating
Commercial Temperature
0 to +70 °C
Temperature
Range
Operating
Industrial Temperature
-40 to +85 °C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs
2




 IDT2308
IDT2308
3.3V ZERO DELAY CLOCK MULTIPLIER
FUNCTION TABLE(1) SELECT INPUT DECODING
S2
S1
CLK A
L
L
Tri-State
L
H
Driven
H
L
Driven
H
H
Driven
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CLK B
Tri-State
Tri-State
Driven
Driven
Output Source
PLL
PLL
REF
PLL
PLL Shut Down
Y
N
Y
N
AVAILABLE OPTIONS FOR IDT2308
Device
Feedback From
IDT2308-1
Bank A or Bank B
IDT2308-1H
Bank A or Bank B
IDT2308-2
Bank A
IDT2308-2
Bank B
IDT2308-2H
Bank A
IDT2308-2H
Bank B
IDT2308-3
Bank A
IDT2308-3
Bank B
IDT2308-4
Bank A or Bank B
IDT2308-5H
Bank A or Bank B
NOTE:
1. Output phase is indeterminant (0° or 180° from input clock).
Bank A Frequency
Reference
Reference
Reference
2 x Reference
Reference
2 x Reference
2 x Reference
4 x Reference
2 x Reference
Reference/2
Bank B Frequency
Reference
Reference
Reference/2
Reference
Reference/2
Reference
Reference or Reference(1)
2 x Reference
2 x Reference
Reference/2
3




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