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CLOCK BUFFER. IDT2308A Datasheet

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CLOCK BUFFER. IDT2308A Datasheet
















IDT2308A BUFFER. Datasheet pdf. Equivalent













Part

IDT2308A

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT2308A 3.3V ZERO DELAY CLOCK MULTIPLIE R COMMERCIAL AND INDUSTRIAL TEMPERATUR E RANGES 3.3V ZERO DELAY CLOCK MULTIPL IER IDT2308A FEATURES: • Phase-Lock Loop Clock Distribution for Applicatio ns ranging from 10MHz to 133MHz operati ng frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback.
Manufacture

Renesas

Datasheet
Download IDT2308A Datasheet


Renesas IDT2308A

IDT2308A; (FBK) pin is used to synchronize the ou tputs to the clock input • Output Ske w <200 ps • Low jitter <200 ps cycle- to-cycle • 1x, 2x, 4x output options (see table): – IDT2308A-1 1x – IDT2 308A-2 1x, 2x – IDT2308A-3 2x, 4x – IDT2308A-4 2x – IDT2308A-1H and -2H for High Drive • No external RC netwo rk required • Operates at 3.3V VDD Available in SOIC and TSSOP packages .


Renesas IDT2308A

DESCRIPTION: The IDT2308A is a high-spee d phase-lock loop (PLL) clock multiplie r. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieve d by aligning the phase between the inc oming clock and the output clock, opera ble within the range of 10 to 133MHz. T he IDT2308A has two banks of four outpu ts each that are c.


Renesas IDT2308A

ontrolled via two select addresses. By p roper selection of input addresses, bot h banks can be put in tri-state mode. I n test mode, the PLL is turned off, and the input clock directly drives the ou tputs for system testing purposes. In t he absence of an input clock, the IDT23 08A enters power down. In this mode, th e device will draw less than 12µA for Commercial Temperat.





Part

IDT2308A

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT2308A 3.3V ZERO DELAY CLOCK MULTIPLIE R COMMERCIAL AND INDUSTRIAL TEMPERATUR E RANGES 3.3V ZERO DELAY CLOCK MULTIPL IER IDT2308A FEATURES: • Phase-Lock Loop Clock Distribution for Applicatio ns ranging from 10MHz to 133MHz operati ng frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback.
Manufacture

Renesas

Datasheet
Download IDT2308A Datasheet




 IDT2308A
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
MULTIPLIER
IDT2308A
FEATURES:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT2308A-1 1x
– IDT2308A-2 1x, 2x
– IDT2308A-3 2x, 4x
– IDT2308A-4 2x
– IDT2308A-1H and -2H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
DESCRIPTION:
The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308A has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT2308A enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than 25µA
for Industrial temperature range, and the outputs are tri-stated.
The IDT2308A is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT2308A is characterized for both Industrial and Commercial opera-
tion.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
16
FBK
2
1
PLL
REF
S2 8
9
S1
Control
Logic
(-2, -3) 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2012 Integrated Device Technology, Inc.
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
AUGUST 2012
DSC 6587/9




 IDT2308A
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
PIN CONFIGURATION
REF
1
CLKA1
2
CLKA2
3
VDD
4
GND
5
CLKB1
6
CLKB2
7
S2
8
16
FBK
15
CLKA4
14
CLKA3
13
VDD
12
GND
11 CLKB4
10
CLKB3
9
S1
SOIC/ TSSOP
TOP VIEW
PIN DESCRIPTION
REF
CLKA1(1)
CLKA2(1)
VDD
GND
CLKB1(1)
CLKB2(1)
S2(2)
S1(2)
CLKB3(1)
CLKB4(1)
GND
VDD
CLKA3(1)
CLKA4(1)
FBK
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Functional Description
Input Reference Clock, 5 Volt Tolerant Input
Clock Output for Bank A
Clock Output for Bank A
3.3V Supply
Ground
Clock Output for Bank B
Clock Output for Bank B
Select Input, Bit 2
Select Input, Bit 1
Clock Output for Bank B
Clock Output for Bank B
Ground
3.3V Supply
Clock Output for Bank A
Clock Output for Bank A
PLL Feedback Input
NOTES:
1. Weak pull down on all outputs.
2. Weak pull ups on these inputs.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max.
Unit
VDD
Supply Voltage Range
–0.5 to +4.6 V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5 V
VI
Input Voltage Range
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50
mA
IO
Continuous Output Current
±50
mA
(VO = 0 to VDD)
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG
StorageTemperatureRange –65 to +150 °C
Operating
Commercial Temperature
0 to +70 °C
Temperature
Range
Operating
Industrial Temperature
-40 to +85 °C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs
2




 IDT2308A
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
FUNCTION TABLE(1) SELECT INPUT DECODING
S2
S1
CLK A
L
L
Tri-State
L
H
Driven
H
L
Driven
H
H
Driven
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CLK B
Tri-State
Tri-State
Driven
Driven
Output Source
PLL
PLL
REF
PLL
PLL Shut Down
Y
N
Y
N
AVAILABLE OPTIONS FOR IDT2308A
Device
Feedback From
IDT2308A-1
Bank A or Bank B
IDT2308A-1H
Bank A or Bank B
IDT2308A-2
Bank A
IDT2308A-2
Bank B
IDT2308A-2H
Bank A
IDT2308A-2H
Bank B
IDT2308A-3
Bank A
IDT2308A-3
Bank B
IDT2308A-4
Bank A or Bank B
NOTE:
1. Output phase is indeterminant (0° or 180° from input clock).
Bank A Frequency
Reference
Reference
Reference
2 x Reference
Reference
2 x Reference
2 x Reference
4 x Reference
2 x Reference
Bank B Frequency
Reference
Reference
Reference/2
Reference
Reference/2
Reference
Reference or Reference(1)
2 x Reference
2 x Reference
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
3




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