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CLOCK BUFFER. IDT2308B Datasheet

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CLOCK BUFFER. IDT2308B Datasheet
















IDT2308B BUFFER. Datasheet pdf. Equivalent













Part

IDT2308B

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


3.3 VOLT ZERO DELAY CLOCK MULTIPLIER DA DTAATSAHSEHEETET 2308B Description The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distributio n and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and th e output clock, operable within the ran ge of 10 to 133MHz.
Manufacture

Renesas

Datasheet
Download IDT2308B Datasheet


Renesas IDT2308B

IDT2308B; . The 2308B has two banks of four output s each that are controlled via two sele ct addresses. By proper selection of in put addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock dire ctly drives the outputs for system test ing purposes. In the absence of an inpu t clock, the 2308B enters power down, a nd the outputs are.


Renesas IDT2308B

tri-stated. In this mode, the device wi ll draw less than 25µA. The 2308B is a vailable in six unique configurations f or both prescaling and multiplication o f the Input REF Clock. (see Available O ptions for 2308B table.) The PLL is clo sed externally to provide more flexibil ity by allowing the user to control the delay between the input clock and the outputs. Features .


Renesas IDT2308B

• Phase-Lock Loop Clock Distribution f or Applications ranging from 10MHz to 1 33MHz operating frequency • Distribut es one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the o utputs to the clock input • Output Sk ew < 200 ps • Low jitter < 200 ps cyc le-to-cycle • 1x, 2x, 4x outpu.





Part

IDT2308B

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


3.3 VOLT ZERO DELAY CLOCK MULTIPLIER DA DTAATSAHSEHEETET 2308B Description The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distributio n and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and th e output clock, operable within the ran ge of 10 to 133MHz.
Manufacture

Renesas

Datasheet
Download IDT2308B Datasheet




 IDT2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
DADTAATSAHSEHEETET
2308B
Description
The 2308B is a high-speed phase-lock loop (PLL) clock
multiplier. It is designed to address high-speed clock
distribution and multiplication applications. The zero delay
is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10
to 133MHz.
The 2308B has two banks of four outputs each that are
controlled via two select addresses. By proper selection of
input addresses, both banks can be put in tri-state mode. In
test mode, the PLL is turned off, and the input clock directly
drives the outputs for system testing purposes. In the
absence of an input clock, the 2308B enters power down,
and the outputs are tri-stated. In this mode, the device will
draw less than 25µA.
The 2308B is available in six unique configurations for both
prescaling and multiplication of the Input REF Clock. (see
Available Options for 2308B table.)
The PLL is closed externally to provide more flexibility by
allowing the user to control the delay between the input
clock and the outputs.
Features
Phase-Lock Loop Clock Distribution for Applications
ranging from 10MHz to 133MHz operating frequency
Distributes one clock input to two banks of four outputs
Separate output enable for each output bank
External feedback (FBK) pin is used to synchronize the
outputs to the clock input
Output Skew < 200 ps
Low jitter < 200 ps cycle-to-cycle
1x, 2x, 4x output options (see Available Options for
2308B table)
No external RC network required
Operates at 3.3 V VDD
Available in 16-SOIC and 16-TSSOP packages
Available in commercial and industrial temperature
ranges
Block Diagram
©2021 Renesas Electronics Corporation
1
R31DS0037EU0300
MAY 21, 2021




 IDT2308B
2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Applications
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
Function Table1 Select Input Decoding
S2 S1 CLKA
L L Tri-state
L H Driven
H L Driven
H H Driven
CLKB
Tri-state
Tri-state
Driven
Driven
Output
Source
PLL
PLL
REF
PLL
PLL Shut
Down
Y
N
Y
N
Note 1: H = HIGH voltage level; L = LOW voltage level
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF1
CLKA12
CLKA22
VDD
GND
CLKB12
CLKB22
S23
S13
CLKB32
CLKB42
GND
VDD
CLKA32
CLKA42
FBK
Pin Description
Input Reference Clock, 5 Volt Tolerant Input.
Clock Output for Bank A.
Clock Output for Bank A.
3.3 V Supply.
Ground.
Clock Output for Bank B.
Clock Output for Bank B.
Select Input, Bit 2.
Select Input, Bit 1.
Clock Output for Bank B.
Clock Output for Bank B.
Ground.
3.3 V Supply.
Clock Output for Bank A.
Clock Output for Bank A.
PLL Feedback Input.
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-up on these inputs.
©2021 Renesas Electronics Corporation
2
R31DS0037EU0300
MAY 21, 2021




 IDT2308B
2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Available Options for 2308B
Device
Feedback From
Bank A Frequency
2308B-1
Bank A or Bank B
Reference
2308B-1H
Bank A or Bank B
Reference
2308B-2
Bank A
Reference
2308B-2
Bank B
2 x Reference
2308B-2H
Bank A
Reference
2308B-2H
Bank B
2 x Reference
2308B-3
Bank A
2 x Reference
2308B-3
Bank B
4 x Reference
2308B-4
Bank A or Bank B
2 x Reference
2308B-5H
Bank A or Bank B
Reference/2
Note 1: Output phase is indeterminant (0° or 180° from input clock).
Absolute Maximum Ratings1
Bank B Frequency
Reference
Reference
Reference/2
Reference
Reference/2
Reference
Reference or Reference1
2 x Reference
2 x Reference
Reference/2
Symbol
VDD
VI2
VI
IIK (VI < 0)
IOK (VO < 0 or VO > VDD)
IO (VO = 0 to VDD)
VDD or GND
TA = 55 °C (in still air only)3
TSTG
Operating Temperature
Operating Temperature
Rating
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range (except REF)
Input Clamp Current
Terminal Voltage with Respect to
GND (inputs VIH 2.5, VIL 2.5)
Continuous Output Current
Continuous Current
Maximum Power Dissipation
Storage Temperature Range
Commercial range
Industrial range
Max.
-0.5 V to +4.6
-0.5 V to +5.5
-0.5 to VDD + 0.5
-50
±50
±50
±100
0.7
-65 to +150
0 to +70
-40 to +85
Unit
V
V
V
mA
mA
mA
mA
W
C
C
C
Notes:
1. Stresses above the ratings listed below can cause permanent damage to the 2308B. These ratings, which are standard
values for commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750
mils.
©2021 Renesas Electronics Corporation
3
R31DS0037EU0300
MAY 21, 2021




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