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CLOCK BUFFER. IDT23S05 Datasheet

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CLOCK BUFFER. IDT23S05 Datasheet
















IDT23S05 BUFFER. Datasheet pdf. Equivalent













Part

IDT23S05

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT23S05 3.3V ZERO DELAY CLOCK BUFFER, S PREAD SPECTRUM COMMERCIAL AND INDUSTRI AL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBL E IDT23S05 FEATURES: • Phase-Lock L oop Clock Distribution • 10MHz to 133 MHz operating frequency • Distributes one clock input to one bank of five ou tputs • Zero Input-Output Delay • O utput Skew < 250ps • Low jit.
Manufacture

Renesas

Datasheet
Download IDT23S05 Datasheet


Renesas IDT23S05

IDT23S05; ter <200 ps cycle-to-cycle • IDT23S05- 1 for Standard Drive • IDT23S05-1H fo r High Drive • No external RC network required • Operates at 3.3V VDD • Power down mode • Spread spectrum com patible • Available in SOIC package DESCRIPTION: The IDT23S05 is a high-spe ed phase-lock loop (PLL) clock buffer, designed to address high-speed clock di stribution applications. The zer.


Renesas IDT23S05

o delay is achieved by aligning the phas e between the incoming clock and the ou tput clock, operable within the range o f 10 to 133MHz. The IDT23S05 is an 8-pi n version of the IDT23S09. IDT23S05 acc epts one reference input, and drives ou t five low skew clocks. The -1H version of this device operates up to 133MHz f requency and has a higher drive than th e -1 device. All p.


Renesas IDT23S05

arts have on-chip PLLs which lock to an input clock on the REF pin. The PLL fee dback is on-chip and is obtained from t he CLKOUT pad. In the absence of an inp ut clock, the IDT23S05 enters power dow n. In this mode, the device will draw l ess than 12µA for Commercial Tempera- ture range and less than 25µA for Indu strial temperature range, the outputs a re tri-stated, and t.





Part

IDT23S05

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT23S05 3.3V ZERO DELAY CLOCK BUFFER, S PREAD SPECTRUM COMMERCIAL AND INDUSTRI AL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBL E IDT23S05 FEATURES: • Phase-Lock L oop Clock Distribution • 10MHz to 133 MHz operating frequency • Distributes one clock input to one bank of five ou tputs • Zero Input-Output Delay • O utput Skew < 250ps • Low jit.
Manufacture

Renesas

Datasheet
Download IDT23S05 Datasheet




 IDT23S05
IDT23S05
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
BUFFER, SPREAD SPECTRUM
COMPATIBLE
IDT23S05
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT23S05-1 for Standard Drive
• IDT23S05-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Spread spectrum compatible
• Available in SOIC package
DESCRIPTION:
The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT23S05 is an 8-pin version of the IDT23S09. IDT23S05 accepts
one reference input, and drives out five low skew clocks. The -1H version
of this device operates up to 133MHz frequency and has a higher drive than
the -1 device. All parts have on-chip PLLs which lock to an input clock on
the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT23S05 enters power down.
In this mode, the device will draw less than 12µA for Commercial Tempera-
ture range and less than 25µA for Industrial temperature range, the outputs
are tri-stated, and the PLL is not running, resulting in a significant reduction
of power.
The IDT23S05 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
REF 1
PLL
Control
Logic
8
CLKOUT
3 CLK1
2 CLK2
5 CLK3
7
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2010 Integrated Device Technology, Inc.
AUGUST 2010
DSC 6381/7




 IDT23S05
IDT23S05
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM
PIN CONFIGURATION
REF
1
CLK2
2
CLK1
3
GND
4
8
CLKOUT
7
CLK4
6
VDD
5
CLK3
SOIC
TOP VIEW
APPLICATIONS:
• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VDD
VI (2)
VI
IIK (VI < 0)
IO (VO = 0 to VDD)
VDD or GND
TA = 55°C
(in still air)(3)
TSTG
Operating
Temperature
Operating
Temperature
Rating
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range
(except REF)
Input Clamp Current
Continuous Output Current
Continuous Current
Maximum Power Dissipation
Max. Unit
–0.5 to +4.6 V
–0.5 to +5.5 V
–0.5 to
V
VDD+0.5
–50
mA
±50
mA
±100
mA
0.7
W
Storage Temperature Range
Commercial Temperature
Range
Industrial Temperature
Range
–65 to +150 °C
0 to +70 °C
-40 to +85 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name
REF(1)
CLK2(2)
CLK1(2)
GND
CLK3(2)
VDD
CLK4(2)
CLKOUT(2)
Pin Number
1
2
3
4
5
6
7
8
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
Type
IN
Out
Out
Ground
Out
PWR
Out
Out
Functional Description
Input reference clock, 5 Volt tolerant input
Output clock
Output clock
Ground
Output clock
3.3V Supply
Output clock
Output clock, internal feedback on this pin
2




 IDT23S05
IDT23S05
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS - COMMERCIAL
Symbol
VDD
TA
CL
CIN
Parameter
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance < 100MHz
Load Capacitance 100MHz - 133MHz
Input Capacitance
Min.
Max.
Unit
3
3.6
V
0
70
°C
30
pF
10
7
pF
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
VIL
Input LOW Voltage Level
VIH
Input HIGH Voltage Level
IIL
Input LOW Current
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
VOL
Output LOW Voltage
Standard Drive
IOL = 8mA
High Drive
IOL = 12mA (-1H)
VOH
Output HIGH Voltage
Standard Drive
IOH = -8mA
High Drive
IOH = -12mA (-1H)
IDD_PD
Power Down Current
REF = 0MHz
IDD
Supply Current
Unloaded Outputs at 66.66MHz
Min.
Max.
Unit
0.8
V
2
V
50
µA
100
µA
0.4
V
2.4
V
12
µA
32
mA
SWITCHING CHARACTERISTICS (23S05-1) - COMMERCIAL(1,2)
Symbol
Parameter
Conditions
Min.
t1
Output Frequency
10pF Load
10
30pF Load
10
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
t3
Rise Time
Measured between 0.8V and 2V
t4
Fall Time
Measured between 0.8V and 2V
t5
Output to Output Skew
All outputs equally loaded
t6
Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
tJ
Cycle-to-Cycle Jitter, pk - pk
Measured at 66.66MHz, loaded outputs
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin —
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
Typ. Max. Unit
— 133 MHz
— 100
50 60
%
— 2.5
ns
— 2.5
ns
— 250
ps
0 ±350 ps
0 700
ps
— 200
ps
1
ms
3




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