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CLOCK BUFFER. IDT23S09E Datasheet

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CLOCK BUFFER. IDT23S09E Datasheet
















IDT23S09E BUFFER. Datasheet pdf. Equivalent













Part

IDT23S09E

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE R ANGES 3.3V ZERO DELAY CLOCK BUFFER, SP READ SPECTRUM COMPATIBLE IDT23S09E FE ATURES: • Phase-Lock Loop Clock Distr ibution • 10MHz to 200MHz operating f requency • Distributes one clock inpu t to one bank of five and one bank of f our outputs • Separate output enable for each output bank • Out.
Manufacture

Renesas

Datasheet
Download IDT23S09E Datasheet


Renesas IDT23S09E

IDT23S09E; put Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT23S09E-1 for Stan dard Drive • IDT23S09E-1H for High Dr ive • No external RC network required • Operates at 3.3V VDD • Spread sp ectrum compatible • Available in SOIC and TSSOP packages FUNCTIONAL BLOCK DI AGRAM DESCRIPTION: The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer, designed to address high.


Renesas IDT23S09E

-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock an d the output clock, operable within the range of 10 to 200MHz. The IDT23S09E i s a 16-pin version of the IDT23S05E. Th e IDT23S09E accepts one reference input , and drives two banks of four low skew clocks. The -1H version of this device operates up to 20.


Renesas IDT23S09E

0MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on th e REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT 23S09E enters power down. In this mode, the device will draw less than 12µA f or Commercial Temperature range and les s than 25µA for Ind.





Part

IDT23S09E

Description

3.3V ZERO DELAY CLOCK BUFFER



Feature


IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE R ANGES 3.3V ZERO DELAY CLOCK BUFFER, SP READ SPECTRUM COMPATIBLE IDT23S09E FE ATURES: • Phase-Lock Loop Clock Distr ibution • 10MHz to 200MHz operating f requency • Distributes one clock inpu t to one bank of five and one bank of f our outputs • Separate output enable for each output bank • Out.
Manufacture

Renesas

Datasheet
Download IDT23S09E Datasheet




 IDT23S09E
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK BUFFER, SPREAD
SPECTRUM COMPATIBLE
IDT23S09E
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 200MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT23S09E-1 for Standard Drive
• IDT23S09E-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Spread spectrum compatible
• Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 200MHz.
The IDT23S09E is a 16-pin version of the IDT23S05E. The IDT23S09E
accepts one reference input, and drives two banks of four low skew clocks.
The -1H version of this device operates up to 200MHz frequency and has
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT23S09E enters power down. In this mode, the device will draw less
than 12µA for Commercial Temperature range and less than 25µA for
Industrial temperature range, and the outputs are tri-stated.
The IDT23S09E is characterized for both Industrial and Commercial
operation.
1
PLL
REF
16
CLKOUT
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
S2 8
S1 9
Control
Logic
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2006 Integrated Device Technology, Inc.
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
MAY 2010
DSC - 6399/11




 IDT23S09E
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
PIN CONFIGURATION
REF
1
CLKA1
2
CLKA2
3
VDD
4
GND
5
CLKB1
6
CLKB2
7
S2
8
16 CLKOUT
15 CLKA4
14 CLKA3
13
VDD
12
GND
11
CLKB4
10
CLKB3
9
S1
SOIC/ TSSOP
TOP VIEW
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max. Unit
VDD
Supply Voltage Range
–0.5 to +4.6 V
VI (2)
Input Voltage Range (REF) –0.5 to +5.5 V
VI
Input Voltage Range
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50
mA
IO (VO = 0 to VDD) ContinuousOutputCurrent
±50
mA
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG
StorageTemperatureRange –65 to +150 °C
Operating
Commercial Temperature
0 to +70 °C
Temperature
Range
Operating
Industrial Temperature
-40 to +85 °C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name
REF(1)
CLKA1(2)
CLKA2(2)
VDD
GND
CLKB1(2)
CLKB2(2)
S2(3)
S1(3)
CLKB3(2)
CLKB4(2)
CLKA3(2)
CLKA4(2)
CLKOUT(2)
Pin Number
1
2
3
4, 13
5, 12
6
7
8
9
10
11
14
15
16
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
Type
Functional Description
IN
Input reference clock, 5 Volt tolerant input
Out
Output clock for bank A
Out
Output clock for bank A
PWR
3.3V Supply
GND
Ground
Out
Output clock for bank B
Out
Output clock for bank B
IN
Select input Bit 2
IN
Select input Bit 1
Out
Output clock for bank B
Out
Output clock for bank B
Out
Output clock for bank A
Out
Output clock for bank A
Out
Output clock, internal feedback on this pin
2




 IDT23S09E
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
S2
S1
L
L
CLKA
Tri-State
CLKB
Tri-State
CLKOUT(2)
Driven
Output Source
PLL
PLL Shut Down
N
L
H
Driven
Tri-State
Driven
PLL
N
H
L
Driven
Driven
Driven
REF
Y
H
H
Driven
Driven
Driven
PLL
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
Min.
Max.
Unit
VIL
Input LOW Voltage Level
0.8
V
VIH
Input HIGH Voltage Level
2
V
IIL
Input LOW Current
VIN = 0V
50
µA
IIH
Input HIGH Current
VIN = VDD
100
µA
VOL
Output LOW Voltage
Standard Drive
IOL = 8mA
0.4
V
High Drive
IOL = 12mA (-1H)
VOH
Output HIGH Voltage
Standard Drive
IOH = -8mA
2.4
V
High Drive
IOH = -12mA (-1H)
IDD_PD
Power Down Current
REF = 0MHz (S2 = S1 = H)
12
µA
IDD
Supply Current
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND
32
mA
OPERATING CONDITIONS - COMMERCIAL
Symbol
Parameter
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance < 100MHz
Load Capacitance 100MHz - 200MHz
CIN
Input Capacitance
Min.
Max.
Unit
3
3.6
V
0
70
°C
30
pF
10
7
pF
SWITCHING CHARACTERISTICS (23S09E-1) - COMMERCIAL(1,2)
Symbol
Parameter
Conditions
Min.
t1 Output Frequency
10pF Load
10
Duty Cycle = t2 ÷ t1
30pF Load
10
Measured at 1.4V, FOUT = 66.66MHz
40
t3 Rise Time
Measured between 0.8V and 2V
t4 Fall Time
Measured between 0.8V and 2V
t5 Output to Output Skew
All outputs equally loaded
t6A Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2
t6B Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 in PLL bypass mode (IDT23S09E only) 1
t7 Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
tJ Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
Typ. Max. Unit
— 200 MHz
— 100
50 60 %
— 2.5 ns
— 2.5 ns
— 250 ps
0 ±350 ps
5 8.7 ns
0 700 ps
— 200 ps
1 ms




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