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LVDS REPEATER. SN65LVDS108 Datasheet

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LVDS REPEATER. SN65LVDS108 Datasheet
















SN65LVDS108 REPEATER. Datasheet pdf. Equivalent













Part

SN65LVDS108

Description

8-PORT LVDS REPEATER



Feature


SN65LVDS108 www.ti.com SLLS399E – NO VEMBER 1999 – REVISED FEBRUARY 2005 8 -PORT LVDS REPEATER FEATURES • One L ine Receiver and Eight Line Drivers Con figured as an 8-Port LVDS Repeater • Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA -644 Standard • Typical Data Signalin g Rates to 400 Mbps or Clock Frequencie s to 400 MHz • Enabling Logi.
Manufacture

Texas Instruments

Datasheet
Download SN65LVDS108 Datasheet


Texas Instruments SN65LVDS108

SN65LVDS108; c Allows Individual Control of Each Driv er Output, Plus All Outputs • Low-Vol tage Differential Signaling With Typica l Output Voltage of 350 mV and a 100- Load • Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL , BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks • Propa gation Delay Times < 4.7 ns • Output Skew Less Than 300 ps and Pa.


Texas Instruments SN65LVDS108

rt-to-Part Skew Less Than 1.5 ns • Tot al Power Dissipation at 200 MHz Typical ly Less Than 330 mW With 8 Channels Ena bled • Driver Outputs or Receiver Inp ut Equals High Impedance When Disabled or With VCC < 1.5 V • Bus-Pin ESD Pro tection Exceeds 12 kV • Packaged in T hin Shrink Small-Outline Package With 2 0-Mil Terminal Pitch DBT PACKAGE (TOP VIEW) GND 1 VCC 2 GND 3 N.


Texas Instruments SN65LVDS108

C 4 ENM 5 ENA 6 ENB 7 ENC 8 END 9 A 10 B 11 ENE 12 ENF 13 ENG 14 ENH 15 NC 16 G ND 17 VCC 18 GND 19 38 NC 37 AY 36 AZ 35 BY 34 BZ 33 CY 32 CZ 31 DY 30 DZ 29 EY 28 EZ 27 FY 26 FZ 25 GY 24 GZ 23 HY 22 HZ 21 NC 20 NC NC – No internal c onnection DESCRIPTION The SN65LVDS108 is configured as one differential line receiver connected to eight differentia l line drivers. Indi.





Part

SN65LVDS108

Description

8-PORT LVDS REPEATER



Feature


SN65LVDS108 www.ti.com SLLS399E – NO VEMBER 1999 – REVISED FEBRUARY 2005 8 -PORT LVDS REPEATER FEATURES • One L ine Receiver and Eight Line Drivers Con figured as an 8-Port LVDS Repeater • Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA -644 Standard • Typical Data Signalin g Rates to 400 Mbps or Clock Frequencie s to 400 MHz • Enabling Logi.
Manufacture

Texas Instruments

Datasheet
Download SN65LVDS108 Datasheet




 SN65LVDS108
SN65LVDS108
www.ti.com
SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005
8-PORT LVDS REPEATER
FEATURES
One Line Receiver and Eight Line Drivers
Configured as an 8-Port LVDS Repeater
Line Receiver and Line Drivers Meet or
Exceed the Requirements of ANSI EIA/TIA-644
Standard
Typical Data Signaling Rates to 400 Mbps or
Clock Frequencies to 400 MHz
Enabling Logic Allows Individual Control of
Each Driver Output, Plus All Outputs
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a 100-
Load
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
Propagation Delay Times < 4.7 ns
Output Skew Less Than 300 ps and
Part-to-Part Skew Less Than 1.5 ns
Total Power Dissipation at 200 MHz Typically
Less Than 330 mW With 8 Channels Enabled
Driver Outputs or Receiver Input Equals High
Impedance When Disabled or With VCC < 1.5 V
Bus-Pin ESD Protection Exceeds 12 kV
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
DBT PACKAGE
(TOP VIEW)
GND 1
VCC 2
GND 3
NC 4
ENM 5
ENA 6
ENB 7
ENC 8
END 9
A 10
B 11
ENE 12
ENF 13
ENG 14
ENH 15
NC 16
GND 17
VCC 18
GND 19
38 NC
37 AY
36 AZ
35 BY
34 BZ
33 CY
32 CZ
31 DY
30 DZ
29 EY
28 EZ
27 FY
26 FZ
25 GY
24 GZ
23 HY
22 HZ
21 NC
20 NC
NC – No internal connection
DESCRIPTION
The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers.
Individual output enables are provided for each output and an additional enable is provided for all outputs.
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling
(LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise
emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
The intended application of this device, and the LVDS signaling technique, is for point-to-point or
point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of
approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The
large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced
signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is
particularly advantageous for implementing system clock or data distribution trees.
The SN65LVDS108 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated




 SN65LVDS108
SN65LVDS108
SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM (POSITIVE LOGIC)
AY
ENA
AZ
ENM
BY
BZ
ENB
CY
ENC
CZ
DY
END
DZ
A
B
EY
ENE
EZ
FY
ENF
FZ
GY
ENG
GZ
HY
ENH
HZ
SELECTION GUIDE TO LVDS SPLITTER
The SN65LVDS108 is one member of a family of LVDS splitters and repeaters. A brief overview of the family is
provided in the following table.
DEVICE
SN65LVDS104
SN65LVDS105
SN65LVDS108
SN65LVDS109
SN65LVDS116
SN65LVDS117
LVDS SPLITTER AND REPEATER FAMILY
NUMBER OF INPUTS NUMBER OF OUTPUTS
1 LVDS
4 LVDS
1 LVTTL
4 LVDS
1 LVDS
8 LVDS
2 LVDS
8 LVDS
1 LVDS
16 LVDS
2 LVDS
16 LVDS
PACKAGE
16-pin D
16-pin D
38-pin DBT
38-pin DBT
64-pin DGG
64-pin DGG
COMMENTS
4-Port LVDS repeater
4-Port TTL-to-LVDS repeater
8-Port LVDS repeater
Dual 4-port LVDS repeater
16-Port LVDS repeater
Dual 8-port LVDS repeater
2




 SN65LVDS108
SN65LVDS108
www.ti.com
SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005
FUNCTION TABLE(1)
INPUTS
VID = VA – VB
X
X
VID100 mV
–100 mV < VID < 100 mV
VID-100 mV
ENM
ENx
L
X
X
L
H
H
H
H
H
H
OUTPUTS
xY
xZ
Z
Z
Z
Z
H
L
?
?
L
H
(1) H = high level, L = low level, Z = high impedance, X = don't care, ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
300 k
A Input
7V
VCC
300 k
B Input
7V
300 k
(ENM Only)
Enable
Inputs
7V
50
300 k
VCC
10 k
5
Y or Z
Output
7V
(ENx Only)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VCC Supply voltage range(2)
Input voltage range
Enable inputs
A, B, Y or Z
Electrostatic discharge, A, B, Y, Z, and GND(3)
Continuous power dissipation
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
UNIT
–0.5 V to 4 V
–0.5 V to 6 V
–0.5 V to 4 V
Class 3, A:12 kV, B: 500 V
See Dissipation Rating Table
–65°C to 150°C
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
DBT
TA 25°C
POWER RATING
1277 mW
DERATING FACTOR(1)
ABOVE TA = 25°C
10.2 mW/°C
TA = 85°C
POWER RATING
644 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) with no air flow.
3




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