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Differential Translator/Repeater. SN65LVDS101 Datasheet

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Differential Translator/Repeater. SN65LVDS101 Datasheet
















SN65LVDS101 Translator/Repeater. Datasheet pdf. Equivalent













Part

SN65LVDS101

Description

Differential Translator/Repeater



Feature


Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design SN65LVDS10 0, SN65LVDT100, SN65LVDS101, SN65LVDT10 1 SLLS516E – AUGUST 2002 – REVISED JULY 2015 SN65LVDx10x Differential Tran slator/Repeater 1 Features •1 Design ed for Signaling Rates ≥ 2 Gbps • T otal Jitter < 65 ps • Low-Power Alter native for the MC100EP16 • Low.
Manufacture

Texas Instruments

Datasheet
Download SN65LVDS101 Datasheet


Texas Instruments SN65LVDS101

SN65LVDS101; 100-ps (Maximum) Part-to-Part Skew • 25 mV of Receiver Input Threshold Hyste resis Over 0-V to 4-V Input Voltage Ran ge • Inputs Electrically Compatible W ith LVPECL, CML, and LVDS Signal Levels • 3.3-V Supply Operation • LVDT In tegrates 110-Ω Terminating Resistor Offered in SOIC and MSOP 2 Applicati ons • Wireless Infrastructure • Tel ecom Infrastructure • Printers 3 .


Texas Instruments SN65LVDS101

Description The SN65LVDS100, SN65LVDT100 , SN65LVDS101, and SN65LVDT101 are high -speed differential receivers and drive rs connected as repeaters. The receiver accepts low-voltage differential signa ling (LVDS), positive-emitter-coupled l ogic (PECL), or current-mode logic (CML ) input signals at rates up to 2 Gbps a nd repeats it as either an LVDS or PECL output signal. Th.


Texas Instruments SN65LVDS101

e signal path through the device is diff erential for low radiated emissions and minimal added jitter. Device Informat ion(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN65LVDS100 SOIC (8) VSSOP (8) 4.90 mm × 3.91 mm 3.00 mm × 3.00 mm SN65LVDT100 SOIC (8) VSSOP (8) 4.90 mm × 3.91 mm 3.00 mm × 3.00 mm SN65 LVDS101 SOIC (8) VSSOP (8) 4.90 mm × 3.91 mm 3.00 mm × 3.00.





Part

SN65LVDS101

Description

Differential Translator/Repeater



Feature


Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design SN65LVDS10 0, SN65LVDT100, SN65LVDS101, SN65LVDT10 1 SLLS516E – AUGUST 2002 – REVISED JULY 2015 SN65LVDx10x Differential Tran slator/Repeater 1 Features •1 Design ed for Signaling Rates ≥ 2 Gbps • T otal Jitter < 65 ps • Low-Power Alter native for the MC100EP16 • Low.
Manufacture

Texas Instruments

Datasheet
Download SN65LVDS101 Datasheet




 SN65LVDS101
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
SN65LVDS100, SN65LVDT100, SN65LVDS101, SN65LVDT101
SLLS516E – AUGUST 2002 – REVISED JULY 2015
SN65LVDx10x Differential Translator/Repeater
1 Features
1 Designed for Signaling Rates 2 Gbps
• Total Jitter < 65 ps
• Low-Power Alternative for the MC100EP16
• Low 100-ps (Maximum) Part-to-Part Skew
• 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Input Voltage Range
• Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels
• 3.3-V Supply Operation
• LVDT Integrates 110-Terminating Resistor
• Offered in SOIC and MSOP
2 Applications
• Wireless Infrastructure
• Telecom Infrastructure
• Printers
3 Description
The SN65LVDS100, SN65LVDT100, SN65LVDS101,
and SN65LVDT101 are high-speed differential
receivers and drivers connected as repeaters. The
receiver accepts low-voltage differential signaling
(LVDS), positive-emitter-coupled logic (PECL), or
current-mode logic (CML) input signals at rates up to
2 Gbps and repeats it as either an LVDS or PECL
output signal. The signal path through the device is
differential for low radiated emissions and minimal
added jitter.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65LVDS100
SOIC (8)
VSSOP (8)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
SN65LVDT100
SOIC (8)
VSSOP (8)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
SN65LVDS101
SOIC (8)
VSSOP (8)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
SN65LVDT101
SOIC (8)
VSSOP (8)
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
FUNCTIONAL DIAGRAM
Dual Eye Diagram
EYE PATTERN
SN65LVDS100 and SN65LVDS101
VCC 8
4
2
A
7
6
B3
VBB
2 Gbps
223 - 1 PRBS
Y
VCC = 3.3 V
Z
VID= 200 mV
VIC = 1.2 V
Vert.Scale= 200 mV/div
SN65LVDT100 and SN65LVDT101
2
A
110 W
B3
7
Y
6Z
1 GHz
Horizontal Scale= 200 ps/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.




 SN65LVDS101
SN65LVDS100, SN65LVDT100, SN65LVDS101, SN65LVDT101
SLLS516E – AUGUST 2002 – REVISED JULY 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (Continued) ........................................ 3
6 Device Options....................................................... 3
7 Pin Configuration and Functions ......................... 3
8 Specifications......................................................... 4
8.1 Absolute Maximum Ratings ...................................... 4
8.2 ESD Ratings.............................................................. 4
8.3 Recommended Operating Conditions....................... 4
8.4 Thermal Information .................................................. 5
8.5 Electrical Characteristics........................................... 5
8.6 Switching Characteristics .......................................... 6
8.7 Typical Characteristics .............................................. 7
9 Parameter Measurement Information ................ 12
10 Detailed Description ........................................... 15
10.1 Overview ............................................................... 15
10.2 Functional Block Diagram ..................................... 15
10.3 Feature Description............................................... 15
10.4 Device Functional Modes...................................... 20
11 Application and Implementation........................ 21
11.1 Application Information.......................................... 21
11.2 Typical Application ................................................ 22
12 Power Supply Recommendations ..................... 30
13 Layout................................................................... 30
13.1 Layout Guidelines ................................................. 30
13.2 Layout Example .................................................... 32
14 Device and Documentation Support ................. 33
14.1 Related Links ........................................................ 33
14.2 Community Resources.......................................... 33
14.3 Trademarks ........................................................... 33
14.4 Electrostatic Discharge Caution ............................ 33
14.5 Glossary ................................................................ 33
15 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
Changes from Revision D (December 2014) to Revision E
Page
• Changed Features From: "Over 0-V to 4-V Common-Mode Range" To: "Over 0-V to 4-V Input Voltage Range" ................ 1
Changes from Revision C (June 2004) to Revision D
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
2
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Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101




 SN65LVDS101
www.ti.com
SN65LVDS100, SN65LVDT100, SN65LVDS101, SN65LVDT101
SLLS516E – AUGUST 2002 – REVISED JULY 2015
5 Description (Continued)
The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The
outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential
transmission lines with nominally 100-characteristic impedance.
The SN65LVDT100 and SN65LVDT101 include a 110-differential line termination resistor for less board space,
fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in
the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in
receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is
not used, it should be unconnected or open.
All devices are characterized for operation from –40°C to 85°C.
6 Device Options
ORDERABLE PART NUMBER
SN65LVDS100D
SN65LVDS100DGK
SN65LVDT100D
SN65LVDT100DGK
SN65LVDS101D
SN65LVDS101DGK
SN65LVDT101D
SN65LVDT101DGK
OUTPUT
LVDS
LVDS
LVDS
LVDS
LVPECL
LVPECL
LVPECL
LVPECL
TERMINATION RESISTOR
VBB
No
Yes
No
Yes
Yes
No
Yes
No
No
Yes
No
Yes
Yes
No
Yes
No
7 Pin Configuration and Functions
SN65LVDS100 and SN65LVDS101
D AND DGK PACKAGE
(TOP VIEW)
SN65LVDT100 and SN65LVDT101
D AND DGK PACKAGE
(TOP VIEW)
NC
1
A
2
B
3
VBB
4
8
VCC
7
Y
6
Z
5
GND
NC
1
A
2
B
3
NC
4
NC = Not Connected
8
VCC
7
Y
6
Z
5
GND
NAME
A
B
GND
NC
VBB
VCC
Y
Z
PIN
SN65LVDS100,
SN65LVDS101
2
3
5
1
4
8
7
6
SN65LVDT100,
SN65LVDT101
2
3
5
1, 4
8
7
6
Pin Functions
I/O
DESCRIPTION
I Differential non-inverting input
I Differential inverting input
— Ground
— No connect
O Voltage reference
— Supply voltage
O Differential non-inverting output
O Differential inverting output
Copyright © 2002–2015, Texas Instruments Incorporated
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3
Product Folder Links: SN65LVDS100 SN65LVDT100 SN65LVDS101 SN65LVDT101




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