DatasheetsPDF.com

ESD Protection. NIV1241 Datasheet

DatasheetsPDF.com

ESD Protection. NIV1241 Datasheet
















NIV1241 Protection. Datasheet pdf. Equivalent













Part

NIV1241

Description

ESD Protection



Feature


ESD Protection with Automotive Short-toB attery Blocking Low Capacitance ESD Pro tection with short−to−battery block ing for Automotive High Speed Data Line s NIV1241 The NIV1241 is designed to protect high speed data lines from ESD as well as short to vehicle battery sit uations. The ultra−low capacitance an d low ESD clamping voltage make this de vice an ideal solution f.
Manufacture

ON Semiconductor

Datasheet
Download NIV1241 Datasheet


ON Semiconductor NIV1241

NIV1241; or protecting voltage sensitive high spe ed data lines while the low RDS(on) FET limits distortion on the signal lines. The flow−through style package allow s for easy PCB layout and matched trace lengths necessary to maintain consiste nt impedance between high speed differe ntial lines such as USB and LVDS protoc ols. Features • Low Capacitance (0.5 5 pF Typical, I/O to G.


ON Semiconductor NIV1241

ND) • Protection for the Following Sta ndards: ♦ IEC 61000−4−2 (Level 4) & ISO 10605 • Integrated MOSFETs: Short−to−Battery Blocking ♦ Sho rt−to−USB VBUS Blocking • Wettabl e Flanks Device for optimal Automated O ptical Inspection (AOI) • NIV Prefix for Automotive and Other Applications R equiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP C.


ON Semiconductor NIV1241

apable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Comp liant Typical Applications • Automoti ve High Speed Signal Pairs • USB 2.0 • LVDS ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Operating Juncti on Temperature Range TJ(max) −55 to + 150 °C Storage Temperature Range TS TG −55 to +150 °C Drain−to−Sou.





Part

NIV1241

Description

ESD Protection



Feature


ESD Protection with Automotive Short-toB attery Blocking Low Capacitance ESD Pro tection with short−to−battery block ing for Automotive High Speed Data Line s NIV1241 The NIV1241 is designed to protect high speed data lines from ESD as well as short to vehicle battery sit uations. The ultra−low capacitance an d low ESD clamping voltage make this de vice an ideal solution f.
Manufacture

ON Semiconductor

Datasheet
Download NIV1241 Datasheet




 NIV1241
ESD Protection with
Automotive Short-to-
Battery Blocking
Low Capacitance ESD Protection with
shorttobattery blocking for Automotive
High Speed Data Lines
NIV1241
The NIV1241 is designed to protect high speed data lines from
ESD as well as short to vehicle battery situations. The ultralow
capacitance and low ESD clamping voltage make this device an ideal
solution for protecting voltage sensitive high speed data lines while
the low RDS(on) FET limits distortion on the signal lines. The
flowthrough style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines such as USB and LVDS protocols.
Features
Low Capacitance (0.55 pF Typical, I/O to GND)
Protection for the Following Standards:
IEC 6100042 (Level 4) & ISO 10605
Integrated MOSFETs:
ShorttoBattery Blocking
ShorttoUSB VBUS Blocking
Wettable Flanks Device for optimal Automated Optical Inspection
(AOI)
NIV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ101
Qualified and PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
Automotive High Speed Signal Pairs
USB 2.0
LVDS
ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ(max) 55 to +150
°C
Storage Temperature Range
TSTG 55 to +150
°C
DraintoSource Voltage
VDSS
30
V
GatetoSource Voltage
VGS
±10
V
Lead Temperature Soldering
IEC 6100042 Contact (ESD)
IEC 6100042 Air (ESD)
TSLD
260
°C
ESD
±8
kV
ESD
±15
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
www.onsemi.com
MARKING
DIAGRAM
WDFNW6
CASE 515AK
24 M
1
24 = Specific Device Code
M = Date Code
PIN CONFIGURATION
AND SCHEMATICS
1
6
6
2
5
3
4
4
(Top View)
Pin 2 5 V
Pin 1
D+ HOST
Pin 3
DHOST
Pin 2 5 V
Pin 6
D+
Pin 4
D
Pin 5 GND
ORDERING INFORMATION
Device
Package
Shipping
NIV1241MTWTAG WDFNW6 3000 / Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2019
1
August, 2020 Rev. 0
Publication Order Number:
NIV1241/D




 NIV1241
NIV1241
ELECTRICAL CHARACTERISTICS (TA = 25_C unless otherwise specified)
Parameter
Symbol
Conditions
Min Typ Max Unit
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (Note 1)
Clamping Voltage TLP (Note 2)
See Figures 5 & 6
Junction Capacitance Match
VRWM
I/O Pin to GND
23.5
V
VBR
IT = 1 mA, I/O Pin to GND
24
25
28
V
IR
VRWM = 24 V, I/O Pin to GND
0.5
mA
VC
IEC6100042, ±8 KV Contact
See Figures 1 & 2
VC
IPP = 8 A
IPP = 16 A
IPP = 8 A
IPP = 16 A
35
V
43
V
4.4
V
7.4
V
D CJ
VR = 0 V, f = 1 MHz between I/O 1 to GND
1.0
%
and I/O 2 to GND
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins and
0.55
pF
GND (Pin 4 to GND, Pin 6 to GND)
DraintoSource Breakdown Voltage
DraintoSource Breakdown Voltage
Temperature Coefficient
Zero Gate Voltage Drain Current
GatetoSource Leakage Current
Gate Threshold Voltage (Note 3)
Gate Threshold Voltage Temperature
Coefficient
VBR(DSS)
VBR(DSS)/
TJ
IDSS
IGSS
VGS(TH)
VGS(TH)/TJ
VGS = 0 V, ID = 100 mA
Reference to 25_C, ID = 100 mA
VGS = 0 V, VDS = 30 V
VDS = 0 V, VGS = ±5 V
VDS = VGS, ID = 100 mA
Reference to 25_C, ID = 100 mA
30
27
V
mV/_C
1.0
mA
±1.0
mA
0.1 1.0 1.5
V
2.5
mV/_C
DraintoSource On Resistance
RDS(on) VGS = 4.5 V, ID = 125 mA
1.4 7.0
W
VGS = 2.5 V, ID = 125 mA
2.3 7.5
Forward Transconductance
gFS
VDS = 3.0 V, ID = 125 mA
80
mS
Switching TurnOn Delay Time (Note 4)
Switching TurnOn Rise Time (Note 4)
td(ON)
tr
VGS = 4.5 V, VDS = 24 V
ID = 125 mA, RG = 10 VW
9
nS
41
nS
Switching TurnOff Delay Time (Note 4) td(OFF)
96
nS
Switching TurnOff Fall Time (Note 4)
tf
72
nS
DraintoSource Forward Diode Voltage
VSD
VGS = 0 V, Is = 125 mA
0.79 0.9
V
3 dB Bandwidth
fBW
RL = 50 W
5
GHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 3 and 4 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 * Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50W, tp = 100 ns, tr = 1 ns, averaging window; t1 = 70 ns to t2 = 90 ns.
3. Pulse test: pulse width 300 mS, duty cycle 2%
4. Switching characteristics are independent of operating junction temperatures.
www.onsemi.com
2




 NIV1241
NIV1241
150
130
110
90
70
50
30
10
10
30
20 0
20 40 60 80 100 120 140
TIME (ns)
Figure 1. Typical IEC6100042 +8kV Contact
ESD Clamping Voltage
30
10
10
30
50
70
90
110
130
150
20 0
20 40 60 80 100 120 140
TIME (ns)
Figure 2. Typical IEC6100042 8kV Contact
ESD Clamping Voltage
IEC6100042 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
1
2
7.5
4
2
4
15
8
3
6
22.5
12
4
8
30
16
Current at
60 ns (A)
2
4
6
8
IEC6100042 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 3. IEC6100042 Spec
tP = 0.7 ns to 1 ns
ESD Gun
DUT
Oscilloscope
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D Characterization of ESD Clamping
Performance.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping
voltage at the device level. ON Semiconductor has
developed a way to examine the entire voltage waveform
across the ESD protection diode over the time domain of
an ESD pulse in the form of an oscilloscope screenshot,
which can be found on the datasheets for all ESD protection
diodes. For more information on how ON Semiconductor
creates these screenshots and how to interpret them please
refer to AND8307/D.
www.onsemi.com
3




Recommended third-party NIV1241 Datasheet







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)