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ESD Protection. NIS2161 Datasheet

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ESD Protection. NIS2161 Datasheet
















NIS2161 Protection. Datasheet pdf. Equivalent













Part

NIS2161

Description

ESD Protection



Feature


NIV2161, NIS2161 ESD Protection with Au tomotive Short-toBattery & Ground Prote ction Low Capacitance ESD Protection w/ short− to−battery and short−to ground Protection for Automotive High Speed Data Lines The NIS/NIV2161 is des igned to protect high speed data lines from ESD as well as short to vehicle ba ttery situations. The ultra−low capac itance and low ESD clamping .
Manufacture

ON Semiconductor

Datasheet
Download NIS2161 Datasheet


ON Semiconductor NIS2161

NIS2161; voltage make this device an ideal soluti on for protecting voltage sensitive hig h speed data lines while the low RDS(on ) FET limits distortion on the signal l ines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain con sistent impedance between high speed di fferential lines such as USB and LVDS p rotocols. Features •.


ON Semiconductor NIS2161

Low Capacitance (0.40 pF Typical, I/O t o GND) • Protection for the Following Standards: IEC 61000−4−2 (Level 4) & ISO 10605 • Integrated MOSFETs for Short−to−Battery and Short−to− Ground Protection • NIV Prefix for Au tomotive and Other Applications Requiri ng Unique Site and Control Change Requi rements; AEC−Q101 Qualified and PPAP Capable • These Devices are Pb−Free, H.


ON Semiconductor NIS2161

alogen Free/BFR Free and are RoHS Compli ant Typical Applications • Automotive High Speed Signal Pairs • USB 2.0/3. 0 • LVDS • APIX 2/3 ABSOLUTE MAXIM UM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit O perating Junction Temperature Range TJ( max) −55 to +150 °C Storage Temper ature Range TSTG −55 to +150 °C D rain−to−Source Voltage VDSS 30 .





Part

NIS2161

Description

ESD Protection



Feature


NIV2161, NIS2161 ESD Protection with Au tomotive Short-toBattery & Ground Prote ction Low Capacitance ESD Protection w/ short− to−battery and short−to ground Protection for Automotive High Speed Data Lines The NIS/NIV2161 is des igned to protect high speed data lines from ESD as well as short to vehicle ba ttery situations. The ultra−low capac itance and low ESD clamping .
Manufacture

ON Semiconductor

Datasheet
Download NIS2161 Datasheet




 NIS2161
NIV2161, NIS2161
ESD Protection with
Automotive Short-to-
Battery & Ground Protection
Low Capacitance ESD Protection w/ short
tobattery and shorttoground
Protection for Automotive High Speed
Data Lines
The NIS/NIV2161 is designed to protect high speed data lines
from ESD as well as short to vehicle battery situations. The ultralow
capacitance and low ESD clamping voltage make this device an ideal
solution for protecting voltage sensitive high speed data lines while
the low RDS(on) FET limits distortion on the signal lines. The
flowthrough style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines such as USB and LVDS protocols.
Features
Low Capacitance (0.40 pF Typical, I/O to GND)
Protection for the Following Standards:
IEC 6100042 (Level 4) & ISO 10605
Integrated MOSFETs for ShorttoBattery and ShorttoGround
Protection
NIV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ101
Qualified and PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
Automotive High Speed Signal Pairs
USB 2.0/3.0
LVDS
APIX 2/3
ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ(max) 55 to +150
°C
Storage Temperature Range
TSTG 55 to +150
°C
DraintoSource Voltage
VDSS
30
V
GatetoSource Voltage
Lead Temperature Soldering
IEC 6100042 Contact (ESD)
IEC 6100042 Air (ESD)
VGS
±10
V
TSLD
260
°C
ESD
±8
kV
ESD
±15
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
www.onsemi.com
WDFN10
CASE 511CA
MARKING
DIAGRAM
V2 MG
G
V2 = Specific Device Code
M = Date Code
G = PbFree Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATICS
10 9 8 7 6
12345
(Top View)
Pin 2 – D+ Host
Pin 4 – DHost
Pin 1 and Pin 10 – Source 1
Pin 3 – 5V
Pin 3 – 5V
Pin 9 – D+
Pin 7 – D
Pin 3 – 5V
Pin 3 – 5V
Pin 5 and Pin 6 – Source 2
Pin 8 – GND
ORDERING INFORMATION
Device
Package
Shipping
NIV2161MTTAG
NIS2161MTTAG
WDFN10
(PbFree)
WDFN10
(PbFree)
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
November, 2018 Rev. 3
Publication Order Number:
NIV2161/D




 NIS2161
NIV2161, NIS2161
ELECTRICAL CHARACTERISTICS (TA = 25_C unless otherwise specified)
Parameter
Symbol
Conditions
Min Typ Max Unit
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
Clamping Voltage (Note 1)
Clamping Voltage TLP (Note 2)
See Figures 5 & 6
Junction Capacitance Match
VRWM
I/O Pin to GND
16
V
VBR
IT = 1 mA, I/O Pin to GND
16.5 23
V
IR
VRWM = 5 V, I/O Pin to GND
1.0
mA
VC
IPP = 1 A, I/O Pin to GND (8/20 ms pulse)
29
V
VC
IEC6100042, ±8 KV Contact
See Figures 1 & 2
VC
IPP = ±8 A
IPP = ±16 A
39
V
66
V
D CJ
VR = 0 V, f = 1 MHz between I/O 1 to GND
1.0
%
and I/O 2 to GND
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins and
0.40
pF
GND (Pin 7 to GND, Pin 9 to GND)
DraintoSource Breakdown Voltage
VBR(DSS) VGS = 0 V, ID = 100 mA
30
V
DraintoSource Breakdown Voltage
Temperature Coefficient
VBR(DSS)/ Reference to 25_C, ID = 100 mA
TJ
27
mV/_C
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V, VDS = 30 V
1.0
mA
GatetoSource Leakage Current
IGSS
VDS = 0 V, VGS = ±5 V
±1.0
mA
Gate Threshold Voltage (Note 3)
VGS(TH) VDS = VGS, ID = 100 mA
0.1 1.0 1.5
V
Gate Threshold Voltage Temperature
Coefficient
VGS(TH)/
TJ
Reference to 25_C, ID = 100 mA
2.5
mV/_C
DraintoSource On Resistance
RDS(on) VGS = 4.5 V, ID = 125 mA
1.4 7.0
W
VGS = 2.5 V, ID = 125 mA
2.3 7.5
Forward Transconductance
gFS
VDS = 3.0 V, ID = 125 mA
80
mS
Switching TurnOn Delay Time (Note 4)
Switching TurnOn Rise Time (Note 4)
td(ON)
tr
VGS = 4.5 V, VDS = 24 V
ID = 125 mA, RG = 10 VW
9
nS
41
nS
Switching TurnOff Delay Time (Note 4) td(OFF)
96
nS
Switching TurnOff Fall Time (Note 4)
tf
72
nS
DraintoSource Forward Diode Voltage
VSD
VGS = 0 V, Is = 125 mA
0.79 0.9
V
3 dB Bandwidth
fBW
RL = 50 W
5
GHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 3 and 4 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 * Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
3. Pulse test: pulse width 300 mS, duty cycle 2%
4. Switching characteristics are independent of operating junction temperatures.
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2




 NIS2161
NIV2161, NIS2161
140
120
100
80
60
40
20
0
20
25 0
25 50 75 100 125 150 175
TIME (ns)
Figure 1. Typical IEC6100042 +8kV Contact
ESD Clamping Voltage
20
0
20
40
60
80
100
120
25 0
25 50 75 100 125 150 175
TIME (ns)
Figure 2. Typical IEC6100042 8kV Contact
ESD Clamping Voltage
IEC6100042 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
1
2
7.5
4
2
4
15
8
3
6
22.5
12
4
8
30
16
Current at
60 ns (A)
2
4
6
8
IEC6100042 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 3. IEC6100042 Spec
tP = 0.7 ns to 1 ns
ESD Gun
DUT
Oscilloscope
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D Characterization of ESD Clamping
Performance.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping
voltage at the device level. ON Semiconductor has
developed a way to examine the entire voltage waveform
across the ESD protection diode over the time domain of
an ESD pulse in the form of an oscilloscope screenshot,
which can be found on the datasheets for all ESD protection
diodes. For more information on how ON Semiconductor
creates these screenshots and how to interpret them please
refer to AND8307/D.
www.onsemi.com
3




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