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Embedded Controller. MEC1723 Datasheet

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Embedded Controller. MEC1723 Datasheet
















MEC1723 Controller. Datasheet pdf. Equivalent













Part

MEC1723

Description

Keyboard and Embedded Controller



Feature


MEC172x Keyboard and Embedded Controller for Notebook PC Operating Conditions • Operating Voltages: 3.3 V and 1.8 V • Operating Temperature Range: -40 o C to 85 oC Low Power Modes • Chip is designed to always operate in Lowest Po wer state during Normal Operation • S upports all 5 ACPI Power States for PC platforms • Supports 2 Chip-level Sle ep Modes: Light Sleep and He.
Manufacture

Microchip

Datasheet
Download MEC1723 Datasheet


Microchip MEC1723

MEC1723; avy Sleep - Low Standby Current in Sleep Modes ARM® Cortex-M4F Embedded Proces sor • Programmable clock frequency up to 48 MHz • Fixed point processor Single 4GByte Addressing Space • Ne sted Vectored Interrupt Controller (NVI C) - Maskable Interrupt Controller - Ma skable hardware wake up events - 8 Leve ls of priority, individually assignable by vector • EC Interrupt A.


Microchip MEC1723

ggregator expands number of Inter- rupt sources supported or reduces number of vectors needed • Complete ARM® Stand ard debug support - JTAG-Based DAP port , comprised of SWJ- DP and AHB-AP debug ger access functions Memory Components - 416KB Code/Data SRAM - 352KB optimize d for code performance - 64KB optimized for data performance - 128 Bytes Batte ry Powered Storage SR.


Microchip MEC1723

AM - 4K bits OTP - In circuit programmab le - ROM - Contains Boot ROM - Contains Runtime APIs for built-in functions - 128KB of ROM space - Internal EEPROM - 4Mbit (512KByte) in-chip SPI Serial Fla sh in specific packages (Refer Internal SPI in Table 1-1) - SST25PF040C - SPI Master controller - Supports Mode 0 an d mode 3 - 24MHz Clocks • 96 MHz Inte rnal PLL • 32 kHz Cl.





Part

MEC1723

Description

Keyboard and Embedded Controller



Feature


MEC172x Keyboard and Embedded Controller for Notebook PC Operating Conditions • Operating Voltages: 3.3 V and 1.8 V • Operating Temperature Range: -40 o C to 85 oC Low Power Modes • Chip is designed to always operate in Lowest Po wer state during Normal Operation • S upports all 5 ACPI Power States for PC platforms • Supports 2 Chip-level Sle ep Modes: Light Sleep and He.
Manufacture

Microchip

Datasheet
Download MEC1723 Datasheet




 MEC1723
MEC172x
Keyboard and Embedded Controller for Notebook PC
Operating Conditions
• Operating Voltages: 3.3 V and 1.8 V
• Operating Temperature Range: -40 oC to 85 oC
Low Power Modes
• Chip is designed to always operate in Lowest
Power state during Normal Operation
• Supports all 5 ACPI Power States for PC plat-
forms
• Supports 2 Chip-level Sleep Modes: Light Sleep
and Heavy Sleep
- Low Standby Current in Sleep Modes
ARM® Cortex-M4F Embedded Processor
• Programmable clock frequency up to 48 MHz
• Fixed point processor
• Single 4GByte Addressing Space
• Nested Vectored Interrupt Controller (NVIC)
- Maskable Interrupt Controller
- Maskable hardware wake up events
- 8 Levels of priority, individually assignable by
vector
• EC Interrupt Aggregator expands number of Inter-
rupt sources supported or reduces number of vec-
tors needed
• Complete ARM® Standard debug support
- JTAG-Based DAP port, comprised of SWJ-
DP and AHB-AP debugger access functions
Memory Components
- 416KB Code/Data SRAM
- 352KB optimized for code performance
- 64KB optimized for data performance
- 128 Bytes Battery Powered Storage SRAM
- 4K bits OTP
- In circuit programmable
- ROM
- Contains Boot ROM
- Contains Runtime APIs for built-in func-
tions
- 128KB of ROM space
- Internal EEPROM
- 4Mbit (512KByte) in-chip SPI Serial Flash in
specific packages (Refer Internal SPI in
Table 1-1)
- SST25PF040C
- SPI Master controller
- Supports Mode 0 and mode 3
- 24MHz
Clocks
• 96 MHz Internal PLL
• 32 kHz Clock Sources
- Internal 32 kHz silicon oscillator
- External 32 kHz crystal (XTAL) source
- External single-ended 32 kHz clock
source
Package Options
- 144 pin WFBGA
- 176 pin WFBGA
Security Features
• Boot ROM Secure Boot Loader
- Hardware Root of Trust (RoT) using Secure
Boot and Immutable code
- Supports 2 Code Images in external SPI
Flash (Primary and Fall back image)
- Authenticates SPI Flash image before load-
ing
- Support AES-256 Encrypted SPI Flash
images
• Hardware Accelerators:
- Multi purpose AES Crypto Engine:
- Support for 128-bit - 256-bit key length
- Supports Battery Authentication applica-
tions
- Digital Signature Algorithm Support
- Support for ECDSA and EC_KCDSA
- Cryptographic Hash Engine
- Support for SHA-1, SHA-256 to SHA-512
- Public Key Crypto Engine
- Hardware support for RSA and Elliptic
Curve asymmetric public key algorithms
- RSA keys length of 1024 to 4096 bits
- ECC Prime Field keys up to 571 bits
- ECC Binary Field keys up to 571 bits
- Microcoded support for standard public
key algorithms
- OTP for storing Keys and IDs
- Lockable on 32 B boundaries to prevent
read access or write access
2020-2021 Microchip Technology Inc.
DS00003583E-page 1




 MEC1723
MEC172x
- True Random Number Generator
- 1 Kbit FIFO
- JTAG Disabled by default
System Host interface
• Enhanced Serial Peripheral Interface (eSPI)
- Intel eSPI Specification compliant
- eSPI Interface Base Spec, Intel Doc.
#327432-004, Rev. 1.0.
- eSPI Compatibility Spec, Intel Doc.
#562633, Rev. 0.6
- Support for Master Attached Flash Sharing
(MAFS)
- Support for Slave Attached Flash Sharing
(SAFS)
- Supports all four channels:
- Peripheral Channel
- Virtual Wires Channel
- Out-of-Band (OOB) Tunneled Message
Channel
- Run-time Flash Access Channel
- Supports EC Bus Master to Host Memory
- Supports up to 66 MHz maximum operating
frequency
• One Serial Peripheral Interface (SPI) Slave
- Quad SPI (half-duplex) or Single wire (full
duplex) support
- Mode 0 and Mode3 operation
- Programmable wait time for response delay
• System to EC Message Interface
- Three Embedded Memory Interfaces
- Provides Two Windows to On-Chip SRAM
for Host Access
- Two Register Mailbox Command Interface
- Mailbox Registers Interface
- Thirty-two 8-bit registers
- Two Register Mailbox Command Inter-
faces
- Two Register SMI Source Interfaces
- Six ACPI Embedded Controller Interfaces
- Five EC Interfaces
- One Power Management Interface
• One Serial Peripheral Interface (SPI) Master Con-
troller
- Dual and Quad I/O Support
- Flexible Clock Rates
- Support for 1.8V and 3.3V slave devices
- SPI Burst Capable
- SPI Controller Operates with Internal DMA
Controller with CRC Generation
- Mappable to the following ports (only 1 port
active at a time)
- 1 shared SPI Interface
DS00003583E-page 2
- 2 General purpose SPI
- 1 Private SPI Interface
- 1 In-Chip SPI
• Two General purpose Serial Peripheral Interface
(SPI) Controllers
- One EC driven Full Duplex Serial Communi-
cation Interface
- Flexible Clock Rates
- SPI burst capable
• 8042 Emulated Keyboard Controller
- 8042 Style Host Interface
- Port 92 Legacy A20M Support
- Fast GATEA20 & Fast CPU_RESET
• 18 x 8 Interrupt Capable Multiplexed Keyboard
Scan Matrix
- Optional Push-Pull Drive for Fast Signal
Switching
• PECI Interface 3.1
- Support Intel’s low voltage PECI
• Port 80 BIOS Debug Port
- Two Ports, Assignable to Any eSPI IO
Address
- 24-bit Timestamp with Adjustable Timebase
- 16-Entry FIFO
Peripheral Features
• Internal DMA Controller
- Hardware or Firmware Flow Control
- Firmware Initiated Memory-to-Memory trans-
fers
- Hardware CRC-32 Generator on Channel 0
- 16-Hardware DMA Channels support five
SMBus Master/Slave Controllers, One Quad
SPI Controller and Two General purpose SPI
Controllers
• I2C/SMBus Controllers
- 5 I2C/SMBus controllers
- Up to 16 Configurable I2C ports
- Full Crossbar switch allows any port to be
connected to any controller
- Supports Promiscuous mode of operation
- Fully Operational on Standby Power
- Multi-Master Capable
- Supports Clock Stretching
- Programmable Bus Speeds
- 1 MHz Capable
- Supports DMA Network Layer
• General Purpose I/O Pins
- Inputs:
- Asynchronous rising and falling edge
wakeup detection Interrupt High or Low
Level
2020-2021 Microchip Technology Inc.




 MEC1723
- Outputs:
- Push Pull or Open Drain output
- Programmable power well emulation
- Pull up or pull down resistor control
- Automatically disabling pull-up resistors
when output driven low
- Automatically disabling pull-down resis-
tors when output driven high
- Programmable drive strength
- Two separate1.8V/3.3V configurable IO
regions
- Group or individual control of GPIO data
- 13- Over voltage tolerant GPIO pins
- Glitch protection and Under-Voltage Protec-
tion on all GPIO pins
- 8 GPIO Pass through ports
• Input Capture and Compare timer
- Six 32-bit Capture Registers
- 16 Input Pins (ICTx)
- Full Crossbar switch allows any port to be
connected to any controller
- 32-bit Free-running timer
- Two 32-bit Compare Registers
- Capture, Compare and Overflow Interrupts
• Universal Asynchronous Receiver Transmitter
(UART)
- Two High Speed NS16C550A Compatible
UARTs with Send/Receive 16-Byte FIFOs
- UART0 - Configurable 2-pin/4-pin/8-pin
- UART1 - Configurable 2-pin/4-pin/8-pin
- Programmable Main Power or Standby
Power Functionality
- Standard Baud Rates to 115.2 Kbps, Custom
Baud Rates to 1.5 Mbps
• Programmable Timer Interface
- Two16-bit Auto-reloading Timer Instances
- 16 bit Pre-Scale divider
- Halt and Reload control
- Auto Reload
- Two 32-bit Auto-reloading Timer Instances
- 16 bit Pre-Scale divider
- Halt and Reload control
- Auto Reload
- Three Operating Modes per Instance: Timer
(Reload or Free-Running) or One-shot.
- Event Mode is not supported
• 32-bit RTOS Timer
- Runs Off 32kHz Clock Source
- Continues Counting in all the Chip Sleep
States regardless of Processor Sleep State
2020-2021 Microchip Technology Inc.
MEC172x
- Counter is Halted when Embedded Controller
is Halted (e.g., JTAG debugger active, break
points)
- Generates wake-capable interrupt event
• Watch Dog Timer (WDT)
- Watchdog reset IRQ vector
• Embedded Reset Engine
- Resets the EC if external VCI_IN0# pin is
held low for a programmed time
• Upto 13 Programmable Pulse Width Modulator
(PWM) outputs
- Multiple Clock Rates
- 16-Bit ON & 16-Bit OFF Counters
• 4 Fan Tachometer Inputs
- 16 Bit Resolution
• Two RPM-Based Fan Speed Controllers
- Each includes one Tach input and one PWM
output
- Each includes one Tach input and one PWM
output
- 3% accurate from 500 RPM to 16k RPM
- Automatic Tachometer feedback
- Aging Fan or Invalid Drive Detection
- Spin Up Routine
- Ramp Rate Control
- RPM based Fan Control Algorithm
• Breathing LED Interface
- 4 Blinking/Breathing LEDs
- Programmable Blink Rates
- Piecewise Linear Breathing LED Output Con-
troller
- Provides for programmable rise and fall
waveforms
- Operational in EC Sleep States
• Optional support for Physically Unclonable Func-
tion (PUF)
- 2K Byte memory reserved for PUF.
• PS2 Controller
- One PS2 controllers
- Two PS2 ports
- Both ports are 5 volt tolerant
• PROCHOT interface with Two instances of the
PowerGuard Technology
- Monitor for single assertions or cumulative
PROCHOT active time
- Interrupt generation for PROCHOT assertion
events
- Support PROCHOT assertions to external
CPU
- PowerGuard Technology monitors total sys-
tem power via dedicated Fast A/D converter
DS00003583E-page 3




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