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Type-C Controller. FUSB301 Datasheet

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Type-C Controller. FUSB301 Datasheet
















FUSB301 Controller. Datasheet pdf. Equivalent













Part

FUSB301

Description

Autonomous USB Type-C Controller



Feature


FUSB301 Autonomous USB Type-C Controlle r with Super Speed Switch Control Desc ription The FUSB301 is a fully autonomo us Type-C controller optimized for <15 W applications. The FUSB301 offers CC l ogic detection for Source Mode, Sink Mo de, Dual Role Port Mode, accessory dete ction support, and dead battery support . The FUSB301 features an external swit ch pin (SS_SW) to .
Manufacture

ON Semiconductor

Datasheet
Download FUSB301 Datasheet


ON Semiconductor FUSB301

FUSB301; enable an external USB Super Speed Switc h without interrupting the processor. T he FUSB301 features an extremely low po wer disable mode as well as low power d uring normal operation. It is available in an ultra thin, 10-Lead TMLP package . www.onsemi.com Bottom View X2QFN10 1 .6x1.2, 0.4P CASE 722AC Features • F ully Autonomous Type−C Controller • Supports Type−C Version.


ON Semiconductor FUSB301

s 1.1 and 1.0 • VDD Operating Range, 3 .0 V − 5.5 V • Low Disable Power: I CC = 2 mA (Max.) • Low Standby Power: ICC = 7 mA (Max.) • Dual Role Port M ode with Optional Accessory Support • Capable of Supporting Try.SNK and Try. SRC • Super Speed Switch Control • Dead Battery Support (SINK Support when No Power Applied) • 2 kV HBM ESD Pro tection • Small Packaging, 10 Lead T.


ON Semiconductor FUSB301

MLP (1.6 mm × 1.2 mm × 0.375 mm) ORDE RING INFORMATION See detailed ordering and shipping information on page 2 of t his data sheet. Applications • Smart phones • Tablets • Notebooks • U ltra Portable Applications © Semicond uctor Components Industries, LLC, 2015 June, 2018 − Rev. 0 Figure 1. Typica l Application 1 Publication Order Numb er: FUSB301/D FUSB301 ORDERIN.




Part

FUSB301

Description

Autonomous USB Type-C Controller



Feature


FUSB301 Autonomous USB Type-C Controlle r with Super Speed Switch Control Desc ription The FUSB301 is a fully autonomo us Type-C controller optimized for <15 W applications. The FUSB301 offers CC l ogic detection for Source Mode, Sink Mo de, Dual Role Port Mode, accessory dete ction support, and dead battery support . The FUSB301 features an external swit ch pin (SS_SW) to .
Manufacture

ON Semiconductor

Datasheet
Download FUSB301 Datasheet




 FUSB301
FUSB301
Autonomous USB Type-C
Controller with Super Speed
Switch Control
Description
The FUSB301 is a fully autonomous Type-C controller optimized
for <15 W applications. The FUSB301 offers CC logic detection for
Source Mode, Sink Mode, Dual Role Port Mode, accessory detection
support, and dead battery support. The FUSB301 features an external
switch pin (SS_SW) to enable an external USB Super Speed Switch
without interrupting the processor. The FUSB301 features an
extremely low power disable mode as well as low power during
normal operation. It is available in an ultra thin, 10-Lead TMLP
package.
www.onsemi.com
Bottom View
X2QFN10 1.6x1.2, 0.4P
CASE 722AC
Features
Fully Autonomous TypeC Controller
Supports TypeC Versions 1.1 and 1.0
VDD Operating Range, 3.0 V 5.5 V
Low Disable Power: ICC = 2 mA (Max.)
Low Standby Power: ICC = 7 mA (Max.)
Dual Role Port Mode with Optional Accessory Support
Capable of Supporting Try.SNK and Try.SRC
Super Speed Switch Control
Dead Battery Support (SINK Support when No Power Applied)
2 kV HBM ESD Protection
Small Packaging, 10 Lead TMLP (1.6 mm × 1.2 mm × 0.375 mm)
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
Applications
Smartphones
Tablets
Notebooks
Ultra Portable Applications
© Semiconductor Components Industries, LLC, 2015
June, 2018 Rev. 0
Figure 1. Typical Application
1
Publication Order Number:
FUSB301/D




 FUSB301
FUSB301
ORDERING INFORMATION
Part Number
Top Mark
Operating
Temperature Range
Package
Packing Method
FUSB301TMX
NU
40 to 85°C
10Lead Ultrathin Molded
Leadless Package (TMLP)
1.6 mm × 1.2 mm × 0.375 mm
Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
BLOCK DIAGRAM
PIN CONFIGURATION
Figure 2. Block Diagram
Figure 3. Pin Assignment (Top Through View)
www.onsemi.com
2




 FUSB301
FUSB301
PIN DESCRIPTIONS
Pin #
Name
USB TypeC Connector Interface
6, 7
CC1, CC2
8
VBUS
4
GND
Power Interface
5
VDD
Signal Interface
1
SDA
2
SCL
3
ID
9
SS_SW
10
INT_N
Type
Description
I/O
Input
Ground
TypeC Configuration Channel
VBUS input pin for attach and detach detection
Ground
Power
Input Supply Voltage
Input
OpenDrain
I/O
OpenDrain
Output
CMOS Output
OpenDrain
Output
I2C serial data signal to be connected to the I2C master
I2C serial clock signal to be connected to the I2C master
Used to Identify if connected device is Source to Sink. The ID Pin can
be used to interface with USB 2.0 Input on the processor.
External Super Speed Switch control without processor interrupt.
Active Low open drain interrupt output used to prompt processor to
read I2C register bits.
Dead Battery
If power is not applied to FUSB301 and it is attached to
a Source device, then the Source would pull up the CC line
connected through the cable. The FUSB301 in response
would turn on the pulldown that will bring the CC voltage
to a range that the Source can detect an attach and turn on
VBUS.
Power Up, Initialization and Reset, Interrupt Operation
When power is first applied, the FUSB301 will power up
in Sink mode with all interrupts masked. The local processor
must configure the FUSB301 to the desired mode and clear
the global interrupt mask bit, INT_MASK. The INT_N pin
is an active low, open drain output. This pin indicates to the
host processor that an interrupt has occurred in the
FUSB301 which needs attention. The INT_N pin is in a high
impedance state by default after powerup or device reset,
and the global interrupt mask (INT_MASK in Control
register) is set. After INT_MASK bit is cleared by the local
processor, the INT_N pin stays high impedance in
preparation of future interrupts. When an interruptible event
occurs, INT_N is driven LOW and is in a high impedance
state again when the processor clears the interrupt by reading
the interrupt registers. Subsequent to the initial power up or
reset; if the processor writes a “1” to global interrupt mask
bit when the system is already powered up, the INT_N pin
stays in a high impedance state and ignores all interrupts
until the global interrupt mask bit is cleared. If an event
happens that would ordinarily cause an interrupt when the
global interrupt mask bit is set, the INT_N pin goes LOW
when the global interrupt mask is cleared.
SuperSpeed Switch Control
For applications that require a SuperSpeed USB switch
(USB3.1 Gen 1), the SS_SW pin will autonomously control
the USB switch, such as the FUSB340TMX, without
interrupting the processor.
Table 1. SUPERSPEED SWITCH TRUTH TABLE
CC1
CC2
Not Connected
Not Connected
Connected to CC
Connected to CC
Not Connected
Not Connected
ORIENT1
0
0
1
1
ORIENT0
0
1
0
1
SS_SW
Low
Low
High
Low
Table 2. ID PIN TRUTH TABLE
TYPE Register (h12, bit 4)
SINK = b0
SINK = b1
Description
SINK Not Detected
SINK Detected
ID
HiZ (default)
Low
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3




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