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Type-C Controller. FUSB301A Datasheet

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Type-C Controller. FUSB301A Datasheet
















FUSB301A Controller. Datasheet pdf. Equivalent













Part

FUSB301A

Description

Autonomous USB Type-C Controller



Feature


.
Manufacture

ON Semiconductor

Datasheet
Download FUSB301A Datasheet


ON Semiconductor FUSB301A

FUSB301A; .


ON Semiconductor FUSB301A

.


ON Semiconductor FUSB301A

.




Part

FUSB301A

Description

Autonomous USB Type-C Controller



Feature


.
Manufacture

ON Semiconductor

Datasheet
Download FUSB301A Datasheet




 FUSB301A
FUSB301A
Autonomous USB Type-C
Controller with
Configurable I2C Address
Description
The FUSB301A is a fully autonomous Type-C controller optimized
for < 15 W applications. The FUSB301A offers CC logic detection for
Source Mode, Sink Mode, DRP, accessory detection support, and dead
battery support. The FUSB301A features configurable I2C address
to support multiple ports per system. The FUSB301A features an
extremely low power disable mode as well as low power during
normal operation. It is available in an ultra thin, 12-Lead TMLP
Package.
Features
Fully Autonomous TypeC Controller Supports TypeC Versions 1.1
and 1.0
VDD Operating Range, 3.0 V 5.5 V
Low Disable Power: ICC = 2.0 mA (Max.)
Low Standby Power: ICC = 7.0 mA (Max.)
DRP Mode with Optional Accessory Support
Configurable I2C Address
Capable of Supporting Try.SNK and Try.SRC
Dead Battery Support (SINK Support when No Power Applied)
2 kV HBM ESD Protection
Small Packaging, 12 Lead TMLP (1.6 mm × 1.6 mm × 0.375 mm)
www.onsemi.com
Bottom View
X2QFN12 1.6x1.6, 0.4P
CASE 722AD
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
Applications
Smartphones
Tablets
Notebooks
Ultra Portable Applications
© Semiconductor Components Industries, LLC, 2015
June, 2018 Rev. 0
Figure 1. Typical Application
1
Publication Order Number:
FUSB301A/D




 FUSB301A
FUSB301A
ORDERING INFORMATION
Part Number
Top Mark
Operating
Temperature Range
Package
Packing Method
12Lead Ultrathin Molded
FUSB301A
NX
40 to 85°C
Leadless Package (TMLP)
Tape and Reel
1.6 mm × 1.6 mm × 0.375 mm
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
BLOCK DIAGRAM
PIN CONFIGURATION
Figure 2. Block Diagram
Figure 3. Pin Assignment (Top Through View)
www.onsemi.com
2




 FUSB301A
FUSB301A
PIN DESCRIPTIONS
Pin #
Name
USB TypeC Connector Interface
1, 2
CC1, CC2
4
VBUS
10
GND
Power Interface
12
VDD
Signal Interface
8
SCL
7
SDA
6
INT_N
9
ID
5
I2CADDR
3
NC1
11
NC2
Type
Description
I/O
Input
Ground
TypeC Configuration Channel
VBUS input pin for attach and detach detection
Ground
Power
Input Supply Voltage
Input
OpenDrain
I/O
OpenDrain
Output
OpenDrain
Output
Input
NC
NC
I2C serial clock signal to be connected to the I2C master
I2C serial data signal to be connected to the I2C master
Active LOW open drain interrupt output used to prompt the processor
to read the I2C register bits
Used to Identify if connected device is Source or Sink. The ID Pin
can be used to interface with USB 2.0 Input on the processor.
Used to change bit 3 of the I2C address so that multiple addresses
can be used in a system where two device addresses conflict
No Connect Tie to Ground or Float
No Connect Tie to Ground or Float
Dead Battery
If power is not applied to FUSB301A and it is attached to
a Source device, then the Source would pull up the CC line
connected through the cable. The FUSB301A in response
would turn on the pulldown that will bring the CC voltage
to a range that the Source can detect an attach and turn on
VBUS.
Power Up, Initialization and Reset, Interrupt Operation
When power is first applied, the FUSB301A will power
up in Sink mode with all interrupts masked. The local
processor must configure the FUSB301A to the desired
mode and clear the global interrupt mask bit, INT_MASK.
The INT_N pin is an active low, open drain output. This pin
indicates to the host processor that an interrupt has occurred
in the FUSB301A which needs attention. The INT_N pin is
in a high impedance state by default after powerup or
device reset, and the global interrupt mask (INT_MASK in
Control register) is set. After INT_MASK bit is cleared by
the local processor, the INT_N pin stays high impedance in
preparation of future interrupts. When an interruptible event
occurs, INT_N is driven LOW and is in a high impedance
state again when the processor clears the interrupt by reading
the interrupt registers. Subsequent to the initial power up or
reset; if the processor writes a “1” to global interrupt mask
bit when the system is already powered up, the INT_N pin
stays in a high impedance state and ignores all interrupts
until the global interrupt mask bit is cleared. If an event
happens that would ordinarily cause an interrupt when the
global interrupt mask bit is set, the INT_N pin goes LOW
when the global interrupt mask is cleared.
Table 1. ID PIN TRUTH TABLE
Type Register (h12, bit 4)
SINK = b0
SINK = b1
Description
SINK Not Detected
SINK Detected
ID
HiZ (default)
Low
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
VBUS
VCC_HDDRP
TSTORAGE
Supply Voltage from VDD
VBUS Supply Voltage
CC pins when configured as Host, Device or Dual Role Port
Storage Temperature Range
Min.
Max.
Unit
0.5
6.0
V
0.5
28
V
0.5
6.0
V
65
+150
°C
www.onsemi.com
3




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