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LINE RECEIVERS. SN55173J Datasheet

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LINE RECEIVERS. SN55173J Datasheet
















SN55173J RECEIVERS. Datasheet pdf. Equivalent













Part

SN55173J

Description

QUADRUPLE DIFFERENTIAL LINE RECEIVERS



Feature


SN55173, SN65173, SN75173 QUADRUPLE DIFF ERENTIAL LINE RECEIVERS D Meet or Exce ed the Requirements of TIA/EIA-422-B, T IA/EIA-423-B, and TIA/EIA-485-A and ITU Recommendations V.10, V.11, X.26, and X.27 D Designed for Multipoint Bus Tran smission on Long Bus Lines in Noisy Env ironments D 3-State Outputs D Common-Mo de Input Voltage Range of – 12 V to 1 2 V D Input Sensitiv.
Manufacture

Texas Instruments

Datasheet
Download SN55173J Datasheet


Texas Instruments SN55173J

SN55173J; ity . . . ± 200 mV D Input Hysteresis . . . 50 mV Typ D High Input Impedance . . . 12 kΩ Min D Operate From Single 5-V Supply D Low Power Requirements D P in-to-Pin Replacement for AM26LS32 SLL S144E – OCTOBER 1980 – REVISED APRI L 2000 SN55173 . . . J PACKAGE SN65173, SN75173 . . . D OR N PACKAGE (TOP VIEW ) 1B 1 1A 2 1Y 3 G4 2Y 5 2A 6 2B 7 GND 8 16 VCC 15 4B 14 4A 13.


Texas Instruments SN55173J

4Y 12 G 11 3Y 10 3A 9 3B SN55173 . . . FK PACKAGE (TOP VIEW) 1A 1B NC VCC 4B description The SN55173, SN65173, and SN75173 are monolithic quadruple diffe rential line receivers with 3-state out puts. They are designed to meet the req uirements of TIA/EIA-422-B, TIA/EIA-423 -B, TIA/EIA-485-A, and several ITU reco mmendations. The standards are for bala nced multipoint bu.


Texas Instruments SN55173J

s transmission at rates up to 10 megabit s per second. The four receivers share two OR enable inputs, one active when h igh, the other active when low. These d evices feature high input impedance, in put hysteresis for increased noise immu nity, and input sensitivity of ± 200 m V over a common-mode input voltage rang e of – 12 V to 12 V. Fail-safe design specifies that if th.





Part

SN55173J

Description

QUADRUPLE DIFFERENTIAL LINE RECEIVERS



Feature


SN55173, SN65173, SN75173 QUADRUPLE DIFF ERENTIAL LINE RECEIVERS D Meet or Exce ed the Requirements of TIA/EIA-422-B, T IA/EIA-423-B, and TIA/EIA-485-A and ITU Recommendations V.10, V.11, X.26, and X.27 D Designed for Multipoint Bus Tran smission on Long Bus Lines in Noisy Env ironments D 3-State Outputs D Common-Mo de Input Voltage Range of – 12 V to 1 2 V D Input Sensitiv.
Manufacture

Texas Instruments

Datasheet
Download SN55173J Datasheet




 SN55173J
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
D Meet or Exceed the Requirements of
TIA/EIA-422-B, TIA/EIA-423-B, and
TIA/EIA-485-A and ITU Recommendations
V.10, V.11, X.26, and X.27
D Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments
D 3-State Outputs
D Common-Mode Input Voltage Range of
– 12 V to 12 V
D Input Sensitivity . . . ± 200 mV
D Input Hysteresis . . . 50 mV Typ
D High Input Impedance . . . 12 kMin
D Operate From Single 5-V Supply
D Low Power Requirements
D Pin-to-Pin Replacement for AM26LS32
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
SN55173 . . . J PACKAGE
SN65173, SN75173 . . . D OR N PACKAGE
(TOP VIEW)
1B 1
1A 2
1Y 3
G4
2Y 5
2A 6
2B 7
GND 8
16 VCC
15 4B
14 4A
13 4Y
12 G
11 3Y
10 3A
9 3B
SN55173 . . . FK PACKAGE
(TOP VIEW)
description
The SN55173, SN65173, and SN75173 are
monolithic quadruple differential line receivers
with 3-state outputs. They are designed to meet
the requirements of TIA/EIA-422-B,
TIA/EIA-423-B, TIA/EIA-485-A, and several ITU
recommendations. The standards are for
balanced multipoint bus transmission at rates up
to 10 megabits per second. The four receivers
share two OR enable inputs, one active when
high, the other active when low. These devices
feature high input impedance, input hysteresis for
increased noise immunity, and input sensitivity of
± 200 mV over a common-mode input voltage
range of – 12 V to 12 V. Fail-safe design specifies
that if the inputs are open circuited, the outputs are
always high. The SN65173 and SN75173 are
designed for optimum performance when used
with the SN75172 or SN75174 quad differential
line drivers.
1Y
3 2 1 20 19
4
18
4A
G5
17 4Y
NC 6
16 NC
2Y 7
15 G
2A 8
14 3Y
9 10 11 12 13
NC – No internal connection
THE SN55173 IS NOT RECOMMENDED
FOR NEW DESIGNS.
The SN55173 is characterized over the full military temperature range of – 55°C to 125°C. The SN65173 is
characterized for operation from –40°C to 85°C. The SN75173 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2000, Texas Instruments Incorporated
1




 SN55173J
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC
SMALL OUTLINE
(D)
PLASTIC
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
PLASTIC DIP
(N)
0°C to 70°C
SN75173D
SN75173N
–40°C to 85°C
SN65173D
SN65173N
–55°C to 125°C
SN55173FK
SN55173J
The D package is available taped and reeled. Add the suffix R to the device type (e.g., SN75173DR).
logic symbol
FUNCTION TABLE
(each receiver)
DIFFERENTIAL
A–B
ENABLES
G
G
OUTPUT
Y
H
X
H
VID 0.2 V
X
L
H
H
X
?
–0.2 V < VID < 0.2 V
X
L
?
H
X
L
VID –0.2 V
X
L
L
X
L
H
Z
X
L
H
Open circuit
H
X
H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
4
G
12
G
1
EN
2
1A
1
1B
6
2A
7
2B
10
3A
9
3B
14
4A
15
4B
3
1Y
5
2Y
11
3Y
13
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN55173J
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
logic diagram (positive logic)
4
G
12
G
2
1A
1
1B
6
2A
7
2B
10
3A
9
3B
14
4A
15
4B
Pin numbers shown are for the D, J, and N packages.
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
3
1Y
5
2Y
11
3Y
13
4Y
schematics of inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
VCC
Input
100 k
NOM
A Pins Only
20 k
NOM
960
NOM
EQUIVALENT OF G OR G INPUT
VCC
8.3 k
NOM
Input
100 k
NOM
B Pins Only
960
NOM
TYPICAL OF ALL OUTPUTS
85
NOM
VCC
Output
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3




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