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NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS. SNJ54HC112J Datasheet

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NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS. SNJ54HC112J Datasheet
















SNJ54HC112J FLIP-FLOPS. Datasheet pdf. Equivalent













Part

SNJ54HC112J

Description

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS



Feature


SN54HC112, SN74HC112 DUAL JĆK NEGATIVE EDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Wide Oper ating Voltage Range of 2 V to 6 V D Out puts Can Drive Up To 10 LSTTL Loads D L ow Power Consumption, 40-µA Max ICC D Typical tpd = 13 ns D ±4-mA Output Dri ve at 5 V D Low Input Current of 1 µA Max description/ordering info.
Manufacture

Texas Instruments

Datasheet
Download SNJ54HC112J Datasheet


Texas Instruments SNJ54HC112J

SNJ54HC112J; rmation The ’HC112 devices contain two independent J-K negative-edge-triggere d flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or re sets the outputs, regardless of the lev els of the other inputs. When PRE and C LR are inactive (high), data at the J a nd K inputs meeting the setup time requ irements are transferred to the outputs on the negative-goi.


Texas Instruments SNJ54HC112J

ng edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level an d is not directly related to the fall t ime of the CLK pulse. Following the hol d-time interval, data at the J and K in puts may be changed without affecting t he levels at the outputs. These versati le flip-flops perform as toggle flip-fl ops by tying J and K high. SN54HC112 . . . J OR W PACKAG.


Texas Instruments SNJ54HC112J

E SN74HC112 . . . D OR N PACKAGE (TOP VI EW) 1CLK 1 1K 2 1J 3 1PRE 4 1Q 5 1Q 6 2Q 7 GND 8 16 VCC 15 1CLR 14 2CLR 13 2 CLK 12 2K 11 2J 10 2PRE 9 2Q SN54HC112 . . . FK PACKAGE (TOP VIEW) 1K 1CLK N C VCC 1CLR 1J 1PRE NC 1Q 1Q 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2CLR 2CLK NC 2K 2J 2Q G ND NC 2Q 2PRE NC − No internal conne ction ORDERING INFO.





Part

SNJ54HC112J

Description

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS



Feature


SN54HC112, SN74HC112 DUAL JĆK NEGATIVE EDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Wide Oper ating Voltage Range of 2 V to 6 V D Out puts Can Drive Up To 10 LSTTL Loads D L ow Power Consumption, 40-µA Max ICC D Typical tpd = 13 ns D ±4-mA Output Dri ve at 5 V D Low Input Current of 1 µA Max description/ordering info.
Manufacture

Texas Instruments

Datasheet
Download SNJ54HC112J Datasheet




 SNJ54HC112J
SN54HC112, SN74HC112
DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 40-µA Max ICC
D Typical tpd = 13 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
description/ordering information
The ’HC112 devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
CLK pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops perform as toggle flip-flops by tying J and
K high.
SN54HC112 . . . J OR W PACKAGE
SN74HC112 . . . D OR N PACKAGE
(TOP VIEW)
1CLK 1
1K 2
1J 3
1PRE 4
1Q 5
1Q 6
2Q 7
GND 8
16 VCC
15 1CLR
14 2CLR
13 2CLK
12 2K
11 2J
10 2PRE
9 2Q
SN54HC112 . . . FK PACKAGE
(TOP VIEW)
1J
1PRE
NC
1Q
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2CLR
2CLK
NC
2K
2J
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC112N
SN74HC112N
−40°C to 85°C
SOIC − D
Tube of 40
Reel of 2500
Reel of 250
SN74HC112D
SN74HC112DR
SN74HC112DT
HC112
CDIP − J
Tube of 25
SNJ54HC112J
SNJ54HC112J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC112W
SNJ54HC112W
LCCC − FK
Tube of 55
SNJ54HC112FK
SNJ54HC112FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




 SNJ54HC112J
SN54HC112, SN74HC112
DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
L
L
Q0 Q0
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
Toggle
H
H
H
X
X
Q0 Q0
This configuration is nonstable; that is, it does not persist
when either PRE or CLR returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE
J
C
C
TG
Q
TG
K
C
C
CLK
CLR
C
C
C
TG
TG
C
C
C
Q
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SNJ54HC112J
SN54HC112, SN74HC112
DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC112
MIN NOM MAX
SN74HC112
UNIT
MIN NOM MAX
VCC Supply voltage
2
5
6
2
5
6V
VCC = 2 V
1.5
1.5
VIH High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 6 V
4.2
4.2
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35 V
VCC = 6 V
1.8
1.8
VI
Input voltage
0
VCC
0
VCC V
VO
Output voltage
0
VCC
0
VCC V
VCC = 2 V
1000
1000
tt‡
Input transition (rise and fall) time
VCC = 4.5 V
500
500 ns
VCC = 6 V
400
400
TA
Operating free-air temperature
−55
125 −40
85 °C
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3




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