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POSITIVE-NAND GATE. SN74HC10-EP Datasheet

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POSITIVE-NAND GATE. SN74HC10-EP Datasheet
















SN74HC10-EP GATE. Datasheet pdf. Equivalent













Part

SN74HC10-EP

Description

TRIPLE 3-INPUT POSITIVE-NAND GATE



Feature


SN74HC10ĆEP TRIPLE 3ĆINPUT POSITIVEĆN AND GATE D Controlled Baseline − One Assembly/Test Site, One Fabrication Si te D Extended Temperature Performance o f −40°C to 125°C D Enhanced Diminis hing Manufacturing Sources (DMS) Suppor t D Enhanced Product-Change Notificatio n D Qualification Pedigree† D Wide Op erating Voltage Range of 2 V to 6 V † Component qualification in acc.
Manufacture

Texas Instruments

Datasheet
Download SN74HC10-EP Datasheet


Texas Instruments SN74HC10-EP

SN74HC10-EP; ordance with JEDEC and industry standard s to ensure reliable operation over an extended temperature range. This includ es, but is not limited to, Highly Accel erated Stress Test (HAST) or biased 85/ 85, temperature cycle, autoclave or unb iased HAST, electromigration, bond inte rmetallic life, and mold compound life. Such qualification testing should not be viewed as justi.


Texas Instruments SN74HC10-EP

fying use of this component beyond speci fied performance and environmental limi ts. SCLS558 − JANUARY 2004 D Outputs Can Drive Up To 10 LSTTL Loads D Low P ower Consumption, 20-µA Max ICC D Typi cal tpd = 9 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D OR PW PACKAGE (TOP VIEW) 1A 1 1B 2 2A 3 2B 4 2C 5 2Y 6 GND 7 14 VCC 13 1C 1 2 1Y 11 3C 10 3B 9 3A 8.


Texas Instruments SN74HC10-EP

3Y description/ordering information Th e SN74HC10 device contains three indepe ndent 3-input NAND gates. It performs t he Boolean function Y = A • B • C o r Y = A + B + C in positive logic. ORD ERING INFORMATION TA PACKAGE‡ ORDE RABLE PART NUMBER TOP-SIDE MARKING SO IC − D −40°C to 125°C TSSOP − P W Tape and reel Tape and reel SN74HC1 0QDREP SN74HC10QPWREP SHC10EP S.





Part

SN74HC10-EP

Description

TRIPLE 3-INPUT POSITIVE-NAND GATE



Feature


SN74HC10ĆEP TRIPLE 3ĆINPUT POSITIVEĆN AND GATE D Controlled Baseline − One Assembly/Test Site, One Fabrication Si te D Extended Temperature Performance o f −40°C to 125°C D Enhanced Diminis hing Manufacturing Sources (DMS) Suppor t D Enhanced Product-Change Notificatio n D Qualification Pedigree† D Wide Op erating Voltage Range of 2 V to 6 V † Component qualification in acc.
Manufacture

Texas Instruments

Datasheet
Download SN74HC10-EP Datasheet




 SN74HC10-EP
SN74HC10ĆEP
TRIPLE 3ĆINPUT POSITIVEĆNAND GATE
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Wide Operating Voltage Range of 2 V to 6 V
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
SCLS558 − JANUARY 2004
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 20-µA Max ICC
D Typical tpd = 9 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D OR PW PACKAGE
(TOP VIEW)
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 VCC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
description/ordering information
The SN74HC10 device contains three independent 3-input NAND gates. It performs the Boolean function
Y = A B C or Y = A + B + C in positive logic.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
−40°C to 125°C
TSSOP − PW
Tape and reel
Tape and reel
SN74HC10QDREP
SN74HC10QPWREP
SHC10EP
SHC10EP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
OUTPUT
Y
H
H
H
L
L
X
X
H
X
L
X
H
X
X
L
H
logic diagram (positive logic)
A
B
Y
C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
1




 SN74HC10-EP
SN74HC10ĆEP
TRIPLE 3ĆINPUT POSITIVEĆNAND GATE
SCLS558 − JANUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage
2
5
6V
VCC = 2 V
1.5
VIH High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 6 V
4.2
VCC = 2 V
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35 V
VCC = 6 V
1.8
VI
Input voltage
0
VCC V
VO
Output voltage
0
VCC V
VCC = 2 V
1000
t/v Input transition rise/fall time
VCC = 4.5 V
500 ns
VCC = 6 V
400
TA
Operating free-air temperature
−40
125 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74HC10-EP
SN74HC10ĆEP
TRIPLE 3ĆINPUT POSITIVEĆNAND GATE
SCLS558 − JANUARY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VI = VIH or VIL
VOL
VI = VIH or VIL
II
VI = VCC or 0
ICC
VI = VCC or 0,
Ci
IOH = −20 µA
IOH = −4 mA
IOH = −5.2 mA
IOL = 20 µA
IOL = 4 mA
IOL = 5.2 mA
IO = 0
VCC
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
TA = 25°C
MIN TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98 4.3
5.48 5.8
0.002 0.1
0.001 0.1
0.001 0.1
0.17 0.26
0.15 0.26
±0.1 ±100
2
3
10
MIN MAX UNIT
1.9
4.4
5.9
V
3.7
5.2
0.1
0.1
0.1 V
0.4
0.4
±1000 nA
40 µA
10 pF
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd
tt
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
Y
VCC
2V
4.5 V
6V
2V
4.5 V
6V
TA = 25°C
MIN TYP MAX
35
95
10
19
9
16
23
75
6
15
5
13
MIN MAX UNIT
145
29 ns
25
110
22 ns
19
operating characteristics, TA = 25°C
PARAMETER
Cpd Power dissipation capacitance per gate
TEST CONDITIONS
No load
TYP UNIT
25 pF
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3




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