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POSITIVE-EDGE-TRIGGERED FLIP-FLOPS. SNJ54HC109FK Datasheet

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POSITIVE-EDGE-TRIGGERED FLIP-FLOPS. SNJ54HC109FK Datasheet
















SNJ54HC109FK FLIP-FLOPS. Datasheet pdf. Equivalent













Part

SNJ54HC109FK

Description

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS



Feature


D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To 10 LS TTL Loads SN54HC109 . . . J OR W PACKAG E SN74HC109 . . . D, N, OR NS PACKAGE ( TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2 J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q SN5 4HC109, SN74HC109 DUAL JĆK POSITIVEĆE DGEĆTRIGGERED FLIPĆFL.
Manufacture

Texas Instruments

Datasheet
Download SNJ54HC109FK Datasheet


Texas Instruments SNJ54HC109FK

SNJ54HC109FK; OPS WITH CLEAR AND PRESET SCLS470A − M ARCH 2003 − REVISED OCTOBER 2003 D Lo w Power Consumption, 40-µA Max ICC D T ypical tpd = 12 ns D ±4-mA Output Driv e at 5 V SN54HC109 . . . FK PACKAGE (TO P VIEW) 1J 1CLR NC VCC 2CLR 1K 1CLK N C 1PRE 1Q 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2J 2 K NC 2CLK 2PRE 1Q GND NC 2Q 2Q NC − No internal connection d.


Texas Instruments SNJ54HC109FK

escription/ordering information These de vices contain two independent J-K posit ive-edge-triggered flip-flops. A low le vel at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, rega rdless of the levels of the other input s. When PRE and CLR are inactive (high) , data at the J and K inputs meeting th e setup-time requirements are transferr ed to the outputs .


Texas Instruments SNJ54HC109FK

on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related dir ectly to the rise time of the clock pul se. Following the hold-time interval, d ata at the J and K inputs can be change d without affecting the levels at the o utputs. These versatile flip-flops can perform as toggle flip-flops by groundi ng K and tying J h.





Part

SNJ54HC109FK

Description

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS



Feature


D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To 10 LS TTL Loads SN54HC109 . . . J OR W PACKAG E SN74HC109 . . . D, N, OR NS PACKAGE ( TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2 J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q SN5 4HC109, SN74HC109 DUAL JĆK POSITIVEĆE DGEĆTRIGGERED FLIPĆFL.
Manufacture

Texas Instruments

Datasheet
Download SNJ54HC109FK Datasheet




 SNJ54HC109FK
D Wide Operating Voltage Range of 2 V to 6 V
D Low Input Current of 1 µA Max
D High-Current Outputs Drive Up To
10 LSTTL Loads
SN54HC109 . . . J OR W PACKAGE
SN74HC109 . . . D, N, OR NS PACKAGE
(TOP VIEW)
1CLR 1
1J 2
1K 3
1CLK 4
1PRE 5
1Q 6
1Q 7
GND 8
16 VCC
15 2CLR
14 2J
13 2K
12 2CLK
11 2PRE
10 2Q
9 2Q
SN54HC109, SN74HC109
DUAL JĆK POSITIVEĆEDGEĆTRIGGERED
FLIPĆFLOPS WITH CLEAR AND PRESET
SCLS470A − MARCH 2003 − REVISED OCTOBER 2003
D Low Power Consumption, 40-µA Max ICC
D Typical tpd = 12 ns
D ±4-mA Output Drive at 5 V
SN54HC109 . . . FK PACKAGE
(TOP VIEW)
1K
1CLK
NC
1PRE
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2J
2K
NC
2CLK
2PRE
NC − No internal connection
description/ordering information
These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE)
or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related
directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be
changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by
grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC109N
SN74HC109N
Tube of 40
SN74HC109D
−40°C to 85°C SOIC − D
Reel of 2500
Reel of 250
SN74HC109DR
SN74HC109DT
HC109
SOP − NS
Reel of 2000 SN74HC109NSR
HC109
CDIP − J
Tube of 25
SNJ54HC109J
SNJ54HC109J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC109W
SNJ54HC109W
LCCC − FK
Tube of 55
SNJ54HC109FK
SNJ54HC109FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




 SNJ54HC109FK
SN54HC109, SN74HC109
DUAL JĆK POSITIVEĆEDGEĆTRIGGERED
FLIPĆFLOPS WITH CLEAR AND PRESET
SCLS470A − MARCH 2003 − REVISED OCTOBER 2003
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
L
L
L
H
H
H
H
L
Toggle
H
H
L
H
Q0 Q0
H
H
H
H
H
L
H
H
L
X
X
Q0 Q0
This configuration is nonstable; that is, it does not persist
when either PRE or CLR returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE
J
C
C
TG
Q
TG
K
CLK
CLR
C
C
C
C
C
TG
TG
C
C
C
Q
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SNJ54HC109FK
SN54HC109, SN74HC109
DUAL JĆK POSITIVEĆEDGEĆTRIGGERED
FLIPĆFLOPS WITH CLEAR AND PRESET
SCLS470A − MARCH 2003 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: FK, J, or W packages . . . . . . . . . . . 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or NS packages . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
SN54HC109
MIN NOM MAX
SN74HC109
UNIT
MIN NOM MAX
VCC Supply voltage
2
5
6
2
5
6V
VCC = 2 V
1.5
1.5
VIH High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 6 V
4.2
4.2
VCC = 2 V
0.3
0.5
VIL
Low-level input voltage
VCC = 4.5 V
VCC = 6 V
0.9
1.35 V
1.2
1.8
VI
Input voltage
0
VCC
0
VCC V
VO
Output voltage
0
VCC
0
VCC V
VCC = 2 V
1000
1000
t/v Input transition rise/fall time
VCC = 4.5 V
500
500 ns
VCC = 6 V
400
400
TA
Operating free-air temperature
−55
125 −40
85 °C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3




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