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D-TYPE FLIP-FLOPS. SNJ54HC174J Datasheet

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D-TYPE FLIP-FLOPS. SNJ54HC174J Datasheet
















SNJ54HC174J FLIP-FLOPS. Datasheet pdf. Equivalent













Part

SNJ54HC174J

Description

HEX D-TYPE FLIP-FLOPS



Feature


D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Contain Six Flip-Flops With Single-Rail Outputs D Applications Include: − Buffer/Storage Registers − Shift Registers − Pattern Generat ors description/ordering in.
Manufacture

Texas Instruments

Datasheet
Download SNJ54HC174J Datasheet


Texas Instruments SNJ54HC174J

SNJ54HC174J; formation These positive-edge-triggered D-type flip-flops have a direct clear ( CLR) input. Information at the data (D) inputs meeting the setup time requirem ents is transferred to the outputs on t he positive-going edge of the clock (CL K) pulse. Clock triggering occurs at a particular voltage level and is not dir ectly related to the transition time of the positive-goin.


Texas Instruments SNJ54HC174J

g edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. SN54HC174, SN74H C174 HEX DĆTYPE FLIPĆFLOPS WITH CLEAR SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003 SN54HC174 . . . J OR W PACKAGE SN74HC174 . . . D, DB, N, NS, O R PW PACKAGE (TOP VIEW) CLR 1 1Q 2 1D 3 2D 4 2Q 5 3D 6 3Q 7 GND 8 16 VCC 15 6Q 14 6D 13 5D 12 5Q 11 .


Texas Instruments SNJ54HC174J

4D 10 4Q 9 CLK SN54HC174 . . . FK PACKA GE (TOP VIEW) 1Q CLR NC VCC 6Q 3 2 1 20 19 1D 4 18 6D 2D 5 17 5D NC 6 16 NC 2Q 7 15 5Q 3D 8 14 4D 9 10 1 1 12 13 3Q GND NC CLK 4Q NC − No in ternal connection ORDERING INFORMATION TA PACKAGE† PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube of 25 SN74HC174N SN74HC174N Tube of 40 SN74HC174D .





Part

SNJ54HC174J

Description

HEX D-TYPE FLIP-FLOPS



Feature


D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 14 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Contain Six Flip-Flops With Single-Rail Outputs D Applications Include: − Buffer/Storage Registers − Shift Registers − Pattern Generat ors description/ordering in.
Manufacture

Texas Instruments

Datasheet
Download SNJ54HC174J Datasheet




 SNJ54HC174J
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 14 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Contain Six Flip-Flops With Single-Rail
Outputs
D Applications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
description/ordering information
These positive-edge-triggered D-type flip-flops
have a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
SN54HC174, SN74HC174
HEX DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003
SN54HC174 . . . J OR W PACKAGE
SN74HC174 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1D 3
2D 4
2Q 5
3D 6
3Q 7
GND 8
16 VCC
15 6Q
14 6D
13 5D
12 5Q
11 4D
10 4Q
9 CLK
SN54HC174 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
1D 4
18 6D
2D 5
17 5D
NC 6
16 NC
2Q 7
15 5Q
3D 8
14 4D
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC174N
SN74HC174N
Tube of 40
SN74HC174D
SOIC − D
Reel of 2500
Reel of 250
SN74HC174DR
SN74HC174DT
HC174
−40°C to 85°C
SOP − NS
SSOP − DB
Reel of 2000
Reel of 2000
SN74HC174NSR
SN74HC174DBR
HC174
HC174
Tube of 90
SN74HC174PW
TSSOP − PW
Reel of 2000
Reel of 250
SN74HC174PWR
SN74HC174PWT
HC174
CDIP − J
Tube of 25
SNJ54HC174J
SNJ54HC174J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC174W
SNJ54HC174W
LCCC − FK
Tube of 55
SNJ54HC174FK
SNJ54HC174FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




 SNJ54HC174J
SN54HC174, SN74HC174
HEX DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR CLK D
OUTPUT
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
Q0
logic diagram (positive logic)
1
CLR
CLK 9
3
1D
1D
C1
R
2 1Q
To Five Other Channels
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SNJ54HC174J
SN54HC174, SN74HC174
HEX DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCLS119D − DECEMBER 1982 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC174
MIN NOM MAX
SN74HC174
UNIT
MIN NOM MAX
VCC Supply voltage
2
5
6
2
5
6V
VCC = 2 V
1.5
1.5
VIH High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 6 V
4.2
4.2
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35 V
VCC = 6 V
1.8
1.8
VI
Input voltage
0
VCC
0
VCC V
VO
Output voltage
0
VCC
0
VCC V
VCC = 2 V
1000
1000
t/v Input transition rise/fall time
VCC = 4.5 V
500
500 ns
VCC = 6 V
400
400
TA
Operating free-air temperature
−55
125 −40
85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
II
ICC
Ci
VI = VIH or VIL
IOH = −20 µA
IOH = −4 mA
IOH = −5.2 mA
VI = VIH or VIL
VI = VCC or 0
VI = VCC or 0,
IOL = 20 µA
IOL = 4 mA
IOL = 5.2 mA
IO = 0
VCC
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
TA = 25°C
MIN TYP MAX
1.9 1.998
4.4 4.499
5.9 5.999
3.98 4.3
5.48 5.8
0.002 0.1
0.001 0.1
0.001 0.1
0.17 0.26
0.15 0.26
±0.1 ±100
8
3
10
SN54HC174
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
SN74HC174
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
UNIT
V
V
nA
µA
pF
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3




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