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BINARY COUNTERS. SN74HC191 Datasheet

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BINARY COUNTERS. SN74HC191 Datasheet
















SN74HC191 COUNTERS. Datasheet pdf. Equivalent













Part

SN74HC191

Description

4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS



Feature


SN54HC191, SN74HC191 4ĆBIT SYNCHRONOUS UP/DOWN BINARY COUNTERS D Wide Operati ng Voltage Range of 2 V to 6 V D Output s Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typ ical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Single Down/Up Count-Control Line D Look-Ahead Circuitry Enhances Speed of Cascaded Counters D Fu.
Manufacture

Texas Instruments

Datasheet
Download SN74HC191 Datasheet


Texas Instruments SN74HC191

SN74HC191; lly Synchronous in Count Modes D Asynchr onously Presettable With Load Control d escription/ordering information The ’ HC191 devices are 4-bit synchronous, re versible, up/down binary counters. Sync hronous counting operation is provided by having all flip-flops clocked simult aneously so that the outputs change coi ncident with each other when instructed by the steering log.


Texas Instruments SN74HC191

ic. This mode of operation eliminates th e output counting spikes normally assoc iated with asynchronous (ripple-clock) counters. The outputs of the four flip- flops are triggered on a low- to high-l evel transition of the clock (CLK) inpu t if the count-enable (CTEN) input is l ow. A high at CTEN inhibits counting. T he direction of the count is determined by the level of t.


Texas Instruments SN74HC191

he down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down. SCLS121D − DE CEMBER 1982 − REVISED OCTOBER 2003 SN 54HC191 . . . J OR W PACKAGE SN74HC191 . . . D, N, OR NS PACKAGE (TOP VIEW) B 1 QB 2 QA 3 CTEN 4 D/U 5 QC 6 QD 7 GND 8 16 VCC 15 A 14 CLK 13 RCO 12 MAX/MIN 11 LOAD 10 C 9D SN54HC191 . . . FK PA CKAGE (TOP VIEW) QB B.





Part

SN74HC191

Description

4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS



Feature


SN54HC191, SN74HC191 4ĆBIT SYNCHRONOUS UP/DOWN BINARY COUNTERS D Wide Operati ng Voltage Range of 2 V to 6 V D Output s Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typ ical tpd = 13 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Single Down/Up Count-Control Line D Look-Ahead Circuitry Enhances Speed of Cascaded Counters D Fu.
Manufacture

Texas Instruments

Datasheet
Download SN74HC191 Datasheet




 SN74HC191
SN54HC191, SN74HC191
4ĆBIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 13 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Single Down/Up Count-Control Line
D Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
D Fully Synchronous in Count Modes
D Asynchronously Presettable With Load
Control
description/ordering information
The ’HC191 devices are 4-bit synchronous,
reversible, up/down binary counters.
Synchronous counting operation is provided by
having all flip-flops clocked simultaneously so that
the outputs change coincident with each other
when instructed by the steering logic. This mode
of operation eliminates the output counting spikes
normally associated with asynchronous
(ripple-clock) counters.
The outputs of the four flip-flops are triggered on
a low- to high-level transition of the clock (CLK)
input if the count-enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U) input. When D/U is low, the counter
counts up, and when D/U is high, it counts down.
SCLS121D − DECEMBER 1982 − REVISED OCTOBER 2003
SN54HC191 . . . J OR W PACKAGE
SN74HC191 . . . D, N, OR NS PACKAGE
(TOP VIEW)
B1
QB 2
QA 3
CTEN 4
D/U 5
QC 6
QD 7
GND 8
16 VCC
15 A
14 CLK
13 RCO
12 MAX/MIN
11 LOAD
10 C
9D
SN54HC191 . . . FK PACKAGE
(TOP VIEW)
QA
CTEN
NC
D/U
QC
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
CLK
RCO
NC
MAX/MIN
LOAD
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC191N
SN74HC191N
Tube of 40
SN74HC191D
−40°C to 85°C SOIC − D
Reel of 2500
Reel of 250
SN74HC191DR
SN74HC191DT
HC191
SOP − NS
Reel of 2000 SN74HC191NSR
HC191
CDIP − J
Tube of 25
SNJ54HC191J
SNJ54HC191J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC191W
SNJ54HC191W
LCCC − FK
Tube of 55
SNJ54HC191FK
SNJ54HC191FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




 SN74HC191
SN54HC191, SN74HC191
4ĆBIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121D − DECEMBER 1982 − REVISED OCTOBER 2003
description/ordering information (continued)
These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that
modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter is dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a
low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with
the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N
dividers simply by modifying the count length with the preset inputs.
Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum
(MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one
complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15)
counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low.
The counters can be cascaded easily by feeding RCO to CTEN of the succeeding counter if parallel clocking
is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed
operation.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74HC191
logic diagram (positive logic)
CTEN 4
D/U 5
CLK 14
LOAD 11
A 15
B1
SN54HC191, SN74HC191
4ĆBIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
SCLS121D − DECEMBER 1982 − REVISED OCTOBER 2003
12
MAX/MIN
13
RCO
S
C1
1D
R
3
QA
S
C1
1D
R
2 QB
C 10
S
C1
1D
R
6 QC
D9
S
C1
1D
R
7
QD
Pin numbers shown are for the D, J, N, NS, and W packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3




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