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UP/DOWN COUNTERS. SN74HC193 Datasheet

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UP/DOWN COUNTERS. SN74HC193 Datasheet
















SN74HC193 COUNTERS. Datasheet pdf. Equivalent













Part

SN74HC193

Description

4-BIT SYNCHRONOUS UP/DOWN COUNTERS



Feature


D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 20 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max SN54HC193 . . . J OR W PA CKAGE SN74HC193 . . . D, N, NS, OR PW P ACKAGE (TOP VIEW) B1 QB 2 QA 3 DOWN 4 UP 5 QC 6 QD 7 GND 8 16 VCC 15 A 14 CL R 13 BO 12 CO 11 LOAD.
Manufacture

Texas Instruments

Datasheet
Download SN74HC193 Datasheet


Texas Instruments SN74HC193

SN74HC193; 10 C 9D SN54HC193, SN74HC193 4ĆBIT SY NCHRONOUS UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR) SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003 D Look-Ahead C ircuitry Enhances Cascaded Counters D F ully Synchronous in Count Modes D Paral lel Asynchronous Load for Modulo-N Coun t Lengths D Asynchronous Clear SN54HC19 3 . . . FK PACKAGE (TOP VIEW) QB B NC VCC A QA DOWN NC UP QC.


Texas Instruments SN74HC193

3 2 1 20 19 4 18 5 17 6 16 7 1 5 8 14 9 10 11 12 13 CLR BO NC CO L OAD QD GND NC D C description/orderin g information NC − No internal conne ction The ’HC193 devices are 4-bit s ynchronous, reversible, up/down binary counters. Synchronous operation is prov ided by having all flip-flops clocked s imultaneously so that the outputs chang e coincidentally with .


Texas Instruments SN74HC193

each other when so instructed by the ste ering logic. This mode of operation eli minates the output counting spikes norm ally associated with asynchronous (ripp le-clock) counters. ORDERING INFORMATI ON TA PACKAGE† ORDERABLE PART NUMB ER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC193N SN74HC193N Tube of 40 SN74HC193D −40°C to 85°C SOIC − D SOP − NS Reel of 250.





Part

SN74HC193

Description

4-BIT SYNCHRONOUS UP/DOWN COUNTERS



Feature


D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 20 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max SN54HC193 . . . J OR W PA CKAGE SN74HC193 . . . D, N, NS, OR PW P ACKAGE (TOP VIEW) B1 QB 2 QA 3 DOWN 4 UP 5 QC 6 QD 7 GND 8 16 VCC 15 A 14 CL R 13 BO 12 CO 11 LOAD.
Manufacture

Texas Instruments

Datasheet
Download SN74HC193 Datasheet




 SN74HC193
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 20 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
SN54HC193 . . . J OR W PACKAGE
SN74HC193 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
B1
QB 2
QA 3
DOWN 4
UP 5
QC 6
QD 7
GND 8
16 VCC
15 A
14 CLR
13 BO
12 CO
11 LOAD
10 C
9D
SN54HC193, SN74HC193
4ĆBIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003
D Look-Ahead Circuitry Enhances Cascaded
Counters
D Fully Synchronous in Count Modes
D Parallel Asynchronous Load for Modulo-N
Count Lengths
D Asynchronous Clear
SN54HC193 . . . FK PACKAGE
(TOP VIEW)
QA
DOWN
NC
UP
QC
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
CLR
BO
NC
CO
LOAD
description/ordering information
NC − No internal connection
The ’HC193 devices are 4-bit synchronous, reversible, up/down binary counters.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change
coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the
output counting spikes normally associated with asynchronous (ripple-clock) counters.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC193N
SN74HC193N
Tube of 40
SN74HC193D
−40°C to 85°C
SOIC − D
SOP − NS
Reel of 2500
Reel of 250
Reel of 2000
SN74HC193DR
SN74HC193DT
SN74HC193NSR
HC193
HC193
Tube of 90
SN74HC193PW
TSSOP − PW
Reel of 2000
Reel of 250
SN74HC193PWR
SN74HC193PWT
HC193
CDIP − J
Tube of 25
SNJ54HC193J
SNJ54HC193J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC193W
SNJ54HC193W
LCCC − FK
Tube of 55
SNJ54HC193FK
SNJ54HC193FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




 SN74HC193
SN54HC193, SN74HC193
4ĆBIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003
description/ordering information (continued)
The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP
or DOWN). The direction of counting is determined by which count input is pulsed while the other count input
is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on
the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers
simply by modifying the count length with the preset inputs.
A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The
clear function is independent of the count and LOAD inputs.
These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output
produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)
output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can
be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74HC193
logic diagram (positive logic)
14
CLR
UP 5
DOWN 4
11
LOAD
15
A
B1
10
C
D9
SN54HC193, SN74HC193
4ĆBIT SYNCHRONOUS UP/DOWN COUNTERS
(DUAL CLOCK WITH CLEAR)
SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003
12 CO
13
BO
S
R
S
C1
1D
R
3
QA
S
C1
1D
R
2
QB
S
C1
1D
R
6
QC
S
C1
1D
R
7 QD
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3




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