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D-Type Flip-Flop. CD54HCT564 Datasheet

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D-Type Flip-Flop. CD54HCT564 Datasheet
















CD54HCT564 Flip-Flop. Datasheet pdf. Equivalent













Part

CD54HCT564

Description

Octal D-Type Flip-Flop



Feature


Data sheet acquired from Harris Semicond uctor SCHS188C January 1998 - Revised A pril 2004 CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564 High-Speed CMOS Logic Octal D-Type Flip-Flop, Thr ee-State Inverting Positive-Edge Trigge red [ /Title (CD74 HC534 , CD74 HCT53 4, CD74 HC564 , CD74 HCT56 Features D escription • Buffered Inputs • Co mmon Three-State Outpu.
Manufacture

Texas Instruments

Datasheet
Download CD54HCT564 Datasheet


Texas Instruments CD54HCT564

CD54HCT564; t-Enable Control • Three-State Output s • Bus Line Driving Capability • Typical Propagation Delay = CL = 15pF , TA = 25oC (Clock 13ns at VCC to Outp ut) = 5V, • Fanout (Over Temperatu re Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operatin g Temperature Range . . . -5.


Texas Instruments CD54HCT564

5oC to 125oC • Balanced Propagation D elay and Transition Times • Signifi cant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Oper ation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT T ypes - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0 .8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at V.


Texas Instruments CD54HCT564

OL, VOH The ’HC534, ’HCT534, ’HC5 64, and ’HCT564 are high speed Octal D-Type Flip-Flops manufactured with sil icon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as th e ability to drive 15 LSTTL loads. Due to the large output drive capability an d the three-state feature, these device s are ideally suited for i.




Part

CD54HCT564

Description

Octal D-Type Flip-Flop



Feature


Data sheet acquired from Harris Semicond uctor SCHS188C January 1998 - Revised A pril 2004 CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564 High-Speed CMOS Logic Octal D-Type Flip-Flop, Thr ee-State Inverting Positive-Edge Trigge red [ /Title (CD74 HC534 , CD74 HCT53 4, CD74 HC564 , CD74 HCT56 Features D escription • Buffered Inputs • Co mmon Three-State Outpu.
Manufacture

Texas Instruments

Datasheet
Download CD54HCT564 Datasheet




 CD54HCT564
Data sheet acquired from Harris Semiconductor
SCHS188C
January 1998 - Revised April 2004
CD54/74HC534, CD54/74HCT534,
CD54/74HC564, CD54/74HCT564
High-Speed CMOS Logic Octal D-Type Flip-Flop,
Three-State Inverting Positive-Edge Triggered
[ /Title
(CD74
HC534
,
CD74
HCT53
4,
CD74
HC564
,
CD74
HCT56
Features
Description
• Buffered Inputs
• Common Three-State Output-Enable Control
• Three-State Outputs
• Bus Line Driving Capability
Typical Propagation Delay =
CL = 15pF, TA = 25oC (Clock
13ns at VCC
to Output)
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed
Octal D-Type Flip-Flops manufactured with silicon gate CMOS
technology. They possess the low power consumption of stan-
dard CMOS integrated circuits, as well as the ability to drive
15 LSTTL loads. Due to the large output drive capability and
the three-state feature, these devices are ideally suited for
interfacing with bus lines in a bus organized system. The two
types are functionally identical and differ only in their pinout
arrangements.
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are positive
edge triggered flip-flops. Data at the D inputs, meeting the
setup and hold time requirements, are inverted and trans-
ferred to the Q outputs on the positive going transition of the
CLOCK input. When a high logic level is applied to the OUT-
PUT ENABLE input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs and
the state of the storage elements.
The HCT logic family is speed, function, and pin compatible
with the standard LS logic family.
Ordering Information
PART NUMBER
CD54HC534F3A
CD54HC564F3A
CD54HCT534F3A
CD54HCT564F3A
CD74HC534E
CD74HC564E
CD74HC564M
CD74HC564M96
CD74HCT534E
CD74HCT564E
CD74HCT564M
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1




 CD54HCT564
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
Pinouts
CD54HC534, CD54HCT534
(CERDIP)
CD74HC534, CD74HCT534
(PDIP)
TOP VIEW
OE 1
Q0 2
D0 3
20 VCC
19 Q7
18 D7
D1 4
17 D6
Q1 5
16 Q6
Q2 6
15 Q5
D2 7
14 D5
D3 8
13 D4
Q3 9
GND 10
12 Q4
11 CP
Functional Diagram
CD54HC564, CD54HCT564
(CERDIP)
CD74HC564, CD74HCT564
(PDIP, SOIC)
TOP VIEW
OE 1
D0 2
D1 3
20 VCC
19 Q0
18 Q1
D2 4
17 Q2
D3 5
16 Q3
D4 6
15 Q4
D5 7
14 Q5
D6 8
13 Q6
D7 9
GND 10
12 Q7
11 CP
D0
D1
D2
D3
D4
D5
D6
D7
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
O7
TRUTH TABLE
INPUTS
OE
CP
Dn
L
H
L
L
L
L
X
H
X
X
H = High Level (Steady State)
L = Low Level (Steady State)
X= Don’t Care
= Transition from Low to High Level
Z = High Impedance State
OUTPUT
Qn
L
H
No Change
Z
2




 CD54HCT564
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
SYMBOL
TEST
CONDITIONS
VI (V) IO (mA)
VCC
(V)
VIH
-
-
2
4.5
6
VIL
-
-
2
4.5
6
VOH VIH or VIL -0.02
2
-0.02
4.5
-0.02
6
-
-
-6
4.5
-7.8
6
VOL VIH or VIL 0.02
2
0.02
4.5
0.02
6
-
-
6
4.5
7.8
6
II
VCC or
-
6
GND
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
1.5
-
-
1.5
-
1.5
-
V
3.15
-
-
3.15
-
3.15
-
V
4.2
-
-
4.2
-
4.2
-
V
-
-
0.5
-
0.5
-
0.5
V
-
-
1.35
-
1.35
-
1.35
V
-
-
1.8
-
1.8
-
1.8
V
1.9
-
-
1.9
-
1.9
-
V
4.4
-
-
4.4
-
4.4
-
V
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
V
3.98
-
-
3.84
-
3.7
-
V
5.48
-
-
5.34
-
5.2
-
V
-
-
0.1
-
0.1
-
0.1
V
-
-
0.1
-
0.1
-
0.1
V
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
V
-
-
0.26
-
0.33
-
0.4
V
-
-
0.26
-
0.33
-
0.4
V
-
-
±0.1
-
±1
-
±1
µA
3




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