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Transparent Latch. CD74HC563 Datasheet

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Transparent Latch. CD74HC563 Datasheet
















CD74HC563 Latch. Datasheet pdf. Equivalent













Part

CD74HC563

Description

Octal Inverting Transparent Latch



Feature


Data sheet acquired from Harris Semicond uctor SCHS187C January 1998 - Revised J uly 2003 CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 High-Speed CMO S Logic Octal Inverting Transparent Lat ch, Three-State Outputs [ /Title (CD74 H C533, CD74H CT533, CD74H C563, CD74H CT563) /Subject (High Speed Features Description • Common Latch-Enable Co ntrol • Common Three.
Manufacture

Texas Instruments

Datasheet
Download CD74HC563 Datasheet


Texas Instruments CD74HC563

CD74HC563; -State Output Enable Control • Buffere d Inputs • Three-State Outputs • Bu s Line Driving Capacity • TCyLp=ic1a5 l pPFr,oTpAag=a2ti5oonCD(eDlaatya=to13O nustpaut tV) CC = 5V, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL L oads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Op erating Temperature Range . . .


Texas Instruments CD74HC563

. -55oC to 125oC • Balanced Propagatio n Delay and Transition Times • Signi cant Power Reduction Compared to LSTT L Logic ICs • HC Types - 2V to 6V Ope ration - High Noise Immunity: NIL = 30% , NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at .


Texas Instruments CD74HC563

VOL, VOH The ’HC533, ’HCT533, ’HC 563, and CD74HCT563 are high-speed Octa l Transparent Latches manufactured with silicon gate CMOS technology. They pos sess the low power consumption of stand ard CMOS integrated circuits, as well a s the ability to drive 15 LSTTL devices . The outputs are transparent to the in puts when the latch enable (LE) is high . When the latch enable .




Part

CD74HC563

Description

Octal Inverting Transparent Latch



Feature


Data sheet acquired from Harris Semicond uctor SCHS187C January 1998 - Revised J uly 2003 CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 High-Speed CMO S Logic Octal Inverting Transparent Lat ch, Three-State Outputs [ /Title (CD74 H C533, CD74H CT533, CD74H C563, CD74H CT563) /Subject (High Speed Features Description • Common Latch-Enable Co ntrol • Common Three.
Manufacture

Texas Instruments

Datasheet
Download CD74HC563 Datasheet




 CD74HC563
Data sheet acquired from Harris Semiconductor
SCHS187C
January 1998 - Revised July 2003
CD54/74HC533, CD54/74HCT533,
CD54/74HC563, CD74HCT563
High-Speed CMOS Logic Octal Inverting
Transparent Latch, Three-State Outputs
[ /Title
(CD74H
C533,
CD74H
CT533,
CD74H
C563,
CD74H
CT563)
/Subject
(High
Speed
Features
Description
• Common Latch-Enable Control
• Common Three-State Output Enable Control
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• TCyLp=ic1a5l pPFr,oTpAag=a2ti5oonCD(eDlaatya=to13Onustpaut tV) CC = 5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are
high-speed Octal Transparent Latches manufactured with
silicon gate CMOS technology. They possess the low power
consumption of standard CMOS integrated circuits, as well as
the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the
three-state outputs. When the output enable (OE) is high the
outputs are in the high impedance state. The latch operation
is independent of the state of the output enable.
The ’HC533 and ’HCT533 are identical in function to the
’HC563 and CD74HCT563 but have different pinouts. The
’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373;
the latter are non-inverting types.
Ordering Information
PART NUMBER
CD54HC533F3A
CD54HC563F3A
CD54HCT533F3A
CD74HC533E
CD74HC563E
CD74HC563M
CD74HCT533E
CD74HCT563E
CD74HCT563M
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




 CD74HC563
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
Pinouts
CD54HC533, CD54HCT533
(CERDIP)
CD74HC533, CD74HCT533
(PDIP)
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
CD54HC563
(CERDIP)
CD74HC563, CD74HCT563
(PDIP, SOIC)
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Functional Block Diagram
HC/HCT533
D0
D1
D2
D3
D4
D5
D6
D7
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
TRUTH TABLE
OUTPUT ENABLE
LATCH ENABLE
DATA
Q OUTPUT
L
H
H
L
L
H
L
H
L
L
l
H
L
L
h
L
H
X
X
Z
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior to
the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
2




 CD74HC563
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
SYMBOL
TEST
CONDITIONS
25oC
VI (V) IO (mA) VCC (V) MIN TYP MAX
VIH
-
-
VIL
-
-
VOH
VOL
II
ICC
VIH or
VIL
-0.02
-0.02
-0.02
-6
-7.8
VIH or
VIL
0.02
0.02
0.02
6
7.8
VCC or
-
GND
VCC or
0
GND
2
1.5 -
-
4.5 3.15 -
-
6
4.2 -
-
2
-
- 0.5
4.5
-
- 1.35
6
-
- 1.8
2
1.9 -
-
4.5 4.4 -
-
6
5.9 -
-
4.5 3.98 -
-
6
5.48 -
-
2
-
- 0.1
4.5
-
- 0.1
6
-
- 0.1
4.5
-
- 0.26
6
-
- 0.26
6
-
- ±0.1
6
-
-
8
-40oC TO 85oC
MIN MAX
1.5
-
3.15
-
4.2
-
-
0.5
-
1.35
-
1.8
1.9
-
4.4
-
5.9
-
3.84
-
5.34
-
-
0.1
-
0.1
-
0.1
-
0.33
-
0.33
-
±1
-
80
-55oC TO 125oC
MIN MAX UNITS
1.5
-
V
3.15
-
V
4.2
-
V
-
0.5
V
-
1.35
V
-
1.8
V
1.9
-
V
4.4
-
V
5.9
-
V
3.7
-
V
5.2
-
V
-
0.1
V
-
0.1
V
-
0.1
V
-
0.4
V
-
0.4
V
-
±1
µA
-
160
µA
3




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