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Shift Register. CD54HC597 Datasheet

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Shift Register. CD54HC597 Datasheet
















CD54HC597 Register. Datasheet pdf. Equivalent













Part

CD54HC597

Description

8-Bit Shift Register



Feature


Data sheet acquired from Harris Semicond uctor SCHS191C January 1998 - Revised O ctober 2003 CD54HC597, CD74HC597, CD74 HCT597 High-Speed CMOS Logic 8-Bit Shif t Register with Input Storage [ /Title (CD74 HC597 , CD74 HCT59 7) /Subject ( High Speed CMOS Features Description • Buffered Inputs • Asynchronous P arallel Load • Fanout (Over Temperatu re Range) - Standard Out.
Manufacture

Texas Instruments

Datasheet
Download CD54HC597 Datasheet


Texas Instruments CD54HC597

CD54HC597; puts . . . . . . . . . . . . . . . 10 LS TTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi de Operating Temperature Range . . . -5 5oC to 125oC • Balanced Propagation D elay and Transition Times • Signific ant Power Reduction Compared to LSTTL L ogic ICs • HC Types - 2V to 6V Operat ion - High Noise Immunity: NIL = 30%, N IH = 30% of VCC at VCC = 5V .


Texas Instruments CD54HC597

• HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility , VIL= 0.8V (Max), VIH = 2V (Min) - CMO S Input Compatibility, Il ≤ 1µA at V OL, VOH The ’HC597 and CD74HCT597 ar e high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bi t parallel-in/serial-in, .


Texas Instruments CD54HC597

serial-out shift register. Each register is controlled by its own clock. A “l ow” on the parallel load input (PL) s hifts parallel stored data asynchronous ly into the shift register. A “low” master input (MR) clears the shift reg ister. Serial input data can also be sy nchronously shifted through the shift r egister when PL is high. Ordering Infor mation PART NUMBER TEMP..




Part

CD54HC597

Description

8-Bit Shift Register



Feature


Data sheet acquired from Harris Semicond uctor SCHS191C January 1998 - Revised O ctober 2003 CD54HC597, CD74HC597, CD74 HCT597 High-Speed CMOS Logic 8-Bit Shif t Register with Input Storage [ /Title (CD74 HC597 , CD74 HCT59 7) /Subject ( High Speed CMOS Features Description • Buffered Inputs • Asynchronous P arallel Load • Fanout (Over Temperatu re Range) - Standard Out.
Manufacture

Texas Instruments

Datasheet
Download CD54HC597 Datasheet




 CD54HC597
Data sheet acquired from Harris Semiconductor
SCHS191C
January 1998 - Revised October 2003
CD54HC597, CD74HC597,
CD74HCT597
High-Speed CMOS Logic
8-Bit Shift Register with Input Storage
[ /Title
(CD74
HC597
,
CD74
HCT59
7)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Buffered Inputs
• Asynchronous Parallel Load
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC597 and CD74HCT597 are high-speed silicon gate
CMOS devices that are pin-compatible with the LSTTL 597
devices. Each device consists of an 8-flip-flop input register
and an 8-bit parallel-in/serial-in, serial-out shift register. Each
register is controlled by its own clock. A “low” on the parallel
load input (PL) shifts parallel stored data asynchronously into
the shift register. A “low” master input (MR) clears the shift
register. Serial input data can also be synchronously shifted
through the shift register when PL is high.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
CD54HC597F3A
-55 to 125
16 Ld CERDIP
CD74HC597E
-55 to 125
16 Ld PDIP
CD74HC597M
-55 to 125
16 Ld SOIC
CD74HC597MT
-55 to 125
16 Ld SOIC
CD74HC597M96
-55 to 125
16 Ld SOIC
CD74HC597NSR
-55 to 125
16 Ld SOP
CD74HCT597E
-55 to 125
16 Ld PDIP
CD74HCT597M
-55 to 125
16 Ld SOIC
CD74HCT597MT
-55 to 125
16 Ld SOIC
CD74HCT597M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC597
(CERDIP)
CD74HC597
(PDIP, SOIC, SOP)
CD74HCT597
(PDIP, SOIC)
TOP VIEW
D1 1
D2 2
D3 3
D4 4
D5 5
D6 6
D7 7
GND 8
16 VCC
15 D0
14 DS
13 PL
12 STCP
11 SHCP
10 MR
9 Q7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




 CD54HC597
CD54HC597, CD74HC597, CD74HCT597
Functional Diagram
DS
15
D0
1
D1
2
D2
PARALLEL
DATA
INPUTS
3
D3
4 8 F/F
D4 STORAGE
5 REG.
D5
6
D6
7
D7
12
STCP
11
SHCP 13
PL 10
MR
14
8-BIT
SHIFT
REG.
9
Q7
FUNCTION TABLE
STCP
SHCP
PL
X
X
MR
FUNCTION
X
Data Loaded to Input Flip-Flops
X
L
H
Data Loaded from Inputs to Shift Register
No Clock Edge
X
L
H
Data Transferred from Input Flip-Flops to Shift Register
X
X
L
L
Invalid Logic, State of Shift Register Indeterminate when
Signals Removed
X
X
H
L
Shift Register Cleared
X
H
H
Shift Register Clocked Qn = Qn-1, Q0 = DS
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, = Transition from Low to High CP Level
2




 CD54HC597
CD54HC597, CD74HC597, CD74HCT597
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . .
64
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
SYMBOL
TEST
CONDITIONS
VI (V) IO (mA)
VCC
(V)
VIH
-
-
2
4.5
6
VIL
-
-
2
4.5
6
VOH VIH or VIL -0.02
2
-0.02
4.5
-0.02
6
-
-
-4
4.5
-5.2
6
VOL VIH or VIL 0.02
2
0.02
4.5
0.02
6
-
-
4
4.5
5.2
6
II
VCC or
-
6
GND
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
1.5
-
-
1.5
-
1.5
-
V
3.15
-
-
3.15
-
3.15
-
V
4.2
-
-
4.2
-
4.2
-
V
-
-
0.5
-
0.5
-
0.5
V
-
-
1.35
-
1.35
-
1.35
V
-
-
1.8
-
1.8
-
1.8
V
1.9
-
-
1.9
-
1.9
-
V
4.4
-
-
4.4
-
4.4
-
V
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
V
3.98
-
-
3.84
-
3.7
-
V
5.48
-
-
5.34
-
5.2
-
V
-
-
0.1
-
0.1
-
0.1
V
-
-
0.1
-
0.1
-
0.1
V
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
V
-
-
0.26
-
0.33
-
0.4
V
-
-
0.26
-
0.33
-
0.4
V
-
-
±0.1
-
±1
-
±1
µA
3




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