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D-TYPE LATCHES. CD74HC573E Datasheet

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D-TYPE LATCHES. CD74HC573E Datasheet
















CD74HC573E LATCHES. Datasheet pdf. Equivalent













Part

CD74HC573E

Description

OCTAL TRANSPARENT D-TYPE LATCHES



Feature


CD54HC573, CD74HC573 OCTAL TRANSPARENT D -TYPE LATCHES WITH 3-STATE OUTPUTS SCLS 454A – FEBRUARY 2001 – REVISED APRI L 2003 D 2-V to 6-V VCC Operation D Wi de Operating Temperature Range of –55 °C to 125°C D 3-State Outputs Directl y Drive Bus Lines D Balanced Propagatio n Delays and Transition Times D Bus Dri ver Outputs Drive Up To 15 LS-TTL Loads D Significant Power Reduc.
Manufacture

Texas Instruments

Datasheet
Download CD74HC573E Datasheet


Texas Instruments CD74HC573E

CD74HC573E; tion Compared to LS-TTL Logic ICs descri ption/ordering information CD54HC573 . . . F PACKAGE CD74HC573 . . . E OR M P ACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE The ’HC573 devices a re octal transparent D-type latches des igned for 2-V to 6-V VCC operation. Wh en the latch-enable .


Texas Instruments CD74HC573E

(LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, t he Q outputs are latched at the logic l evels of the D inputs. A buffered outp ut-enable (OE) input can be used to pla ce the eight outputs in either a normal logic state (high or low) or the high- impedance state. In the high-impedance state, the outputs neither load nor dri ve the bus lines s.


Texas Instruments CD74HC573E

ignificantly. The high-impedance state a nd increased drive provide the capabili ty to drive bus lines without interface or pullup components. OE does not aff ect the internal operations of the latc hes. Old data can be retained or new da ta can be entered while the outputs are in the high-impedance state. To ensur e the high-impedance state during power up or power down,.




Part

CD74HC573E

Description

OCTAL TRANSPARENT D-TYPE LATCHES



Feature


CD54HC573, CD74HC573 OCTAL TRANSPARENT D -TYPE LATCHES WITH 3-STATE OUTPUTS SCLS 454A – FEBRUARY 2001 – REVISED APRI L 2003 D 2-V to 6-V VCC Operation D Wi de Operating Temperature Range of –55 °C to 125°C D 3-State Outputs Directl y Drive Bus Lines D Balanced Propagatio n Delays and Transition Times D Bus Dri ver Outputs Drive Up To 15 LS-TTL Loads D Significant Power Reduc.
Manufacture

Texas Instruments

Datasheet
Download CD74HC573E Datasheet




 CD74HC573E
CD54HC573, CD74HC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS454A – FEBRUARY 2001 – REVISED APRIL 2003
D 2-V to 6-V VCC Operation
D Wide Operating Temperature Range of
–55°C to 125°C
D 3-State Outputs Directly Drive Bus Lines
D Balanced Propagation Delays and
Transition Times
D Bus Driver Outputs Drive Up To 15 LS-TTL
Loads
D Significant Power Reduction Compared to
LS-TTL Logic ICs
description/ordering information
CD54HC573 . . . F PACKAGE
CD74HC573 . . . E OR M PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 VCC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
The ’HC573 devices are octal transparent D-type
latches designed for 2-V to 6-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E Tube
CD74HC573E
CD74HC573E
Tube
–55°C to 125°C SOIC – M
Tape and reel
CD74HC573M
CD74HC573M96
HC573M
CDIP – F Tube
CD54HC573F3A CD54HC573F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




 CD74HC573E
CD54HC573, CD74HC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS454A FEBRUARY 2001 REVISED APRIL 2003
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE 1
LE 11
C1
2
1D
1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 CD74HC573E
CD54HC573, CD74HC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS454A FEBRUARY 2001 REVISED APRIL 2003
recommended operating conditions (see Note 3)
TA = 25°C
MIN MAX
TA = 55°C
TO 125°C
MIN MAX
TA = 40°C
TO 85°C
MIN MAX
UNIT
VCC Supply voltage
2
6
2
6
2
6V
VCC = 2 V
1.5
1.5
1.5
VIH High-level input voltage
VCC = 4.5 V
3.15
3.15
3.15
V
VCC = 6 V
4.2
4.2
4.2
VCC = 2 V
0.5
0.5
0.5
VIL Low-level input voltage
VCC = 4.5 V
1.35
1.35
1.35 V
VCC = 6 V
1.8
1.8
1.8
VI Input voltage
0 VCC
0 VCC
0 VCC V
VO Output voltage
0 VCC
0 VCC
0 VCC V
VCC = 2 V
1000
1000
1000
tt
Input transition (rise and fall) time
VCC = 4.5 V
500
500
500 ns
VCC = 6 V
400
400
400
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
II
IOZ
ICC
Ci
Co
VI = VIH or VIL
VI = VIH or VIL
VI = VCC or 0
VO = VCC or 0
VI = VCC or 0,
IOH = 20 µA
IOH = 6 mA
IOH = 7.8 mA
IOL = 20 µA
IOL = 6 mA
IOL = 7.8 mA
IO = 0
VCC
2V
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
6V
TA = 25°C
MIN MAX
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
8
10
20
TA = 55°C
TO 125°C
MIN MAX
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1
±10
160
10
20
TA = 40°C
TO 85°C
MIN MAX
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1
±5
80
10
20
UNIT
V
V
µA
µA
µA
pF
pF
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3




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