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POSITIVE-NAND GATE. SN74AUC1G00 Datasheet

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POSITIVE-NAND GATE. SN74AUC1G00 Datasheet






SN74AUC1G00 GATE. Datasheet pdf. Equivalent




SN74AUC1G00 GATE. Datasheet pdf. Equivalent





Part

SN74AUC1G00

Description

SINGLE 2-INPUT POSITIVE-NAND GATE



Feature


www.ti.com SN74AUC1G00 SINGLE 2-INPUT P OSITIVE-NAND GATE SCES368O – SEPTEMBE R 2001 – REVISED JANUARY 2007 FEATUR ES • Available in the Texas Instrume nts NanoFree™ Package • Optimized f or 1.8-V Operation and Is 3.6-V I/O Tol erant to Support Mixed-Mode Signal Oper ation • Ioff Supports Partial-Power-D own Mode Operation • Sub 1-V Operable • Max tpd of 2.2 ns at 1.8 V •.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G00 Datasheet


Texas Instruments SN74AUC1G00

SN74AUC1G00; Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V • Lat ch-Up Performance Exceeds 100 mA Per JE SD 78, Class II • ESD Protection Exce eds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115 -A) – 1000-V Charged-Device Model (C1 01) DBV PACKAGE (TOP VIEW) DCK PACKAG E (TOP VIEW) DRL PACKAGE (TOP VIEW) Y ZP PACKAGE (BOTTOM VIEW) A 1 .


Texas Instruments SN74AUC1G00

B 2 5 VCC A1 B2 5 VCC A1 B2 5 VC C GND 3 4 Y GND 3 4 Y B2 A 1 5 VCC G ND 3 4Y GND 3 4 Y See mechanical drawings for dimensions. DESCRIPTION T his single 2-input positive-NAND gate i s operational at 0.8-V to 2.7-V VCC, bu t is designed specifically for 1.65-V t o 1.95-V VCC operation. The SN74AUC1G00 performs the Boolean function Y = A B or Y = A + B in .


Texas Instruments SN74AUC1G00

positive logic. NanoFree™ package tech nology is a major breakthrough in IC pa ckaging concepts, using the die as the package. This device is fully specified for partial-power-down applications us ing Ioff. The Ioff circuitry disables t he outputs, preventing damaging current backflow through the device when it is powered down. For more information abo ut AUC Little Logic .

Part

SN74AUC1G00

Description

SINGLE 2-INPUT POSITIVE-NAND GATE



Feature


www.ti.com SN74AUC1G00 SINGLE 2-INPUT P OSITIVE-NAND GATE SCES368O – SEPTEMBE R 2001 – REVISED JANUARY 2007 FEATUR ES • Available in the Texas Instrume nts NanoFree™ Package • Optimized f or 1.8-V Operation and Is 3.6-V I/O Tol erant to Support Mixed-Mode Signal Oper ation • Ioff Supports Partial-Power-D own Mode Operation • Sub 1-V Operable • Max tpd of 2.2 ns at 1.8 V •.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G00 Datasheet




 SN74AUC1G00
www.ti.com
SN74AUC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES368O – SEPTEMBER 2001 – REVISED JANUARY 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.2 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
A
1
B
2
5
VCC
A1
B2
5
VCC
A1
B2
5 VCC
GND 3 4 Y
GND 3 4 Y
B2
A 1 5 VCC
GND 3
4Y
GND
3
4
Y
See mechanical drawings for dimensions.
DESCRIPTION
This single 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC1G00 performs the Boolean function Y = A B or Y = A + B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
ORDERING INFORMATION
TA
PACKAGE (1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUC1G00YZPR
_ _ _UA_
–40°C to 85°C SOT (SOT-23) – DBV
SOT (SC-70) – DCK
Reel of 3000
Reel of 3000
SN74AUC1G00DBVR
SN74AUC1G00DCKR
U00_
UA_
SOT (SOT-553) – DRL
Reel of 4000 SN74AUC1G00DRLR
UA_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2007, Texas Instruments Incorporated




 SN74AUC1G00
SN74AUC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES368O – SEPTEMBER 2001 – REVISED JANUARY 2007
FUNCTION TABLE
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
L
H
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
A
2
B
4
Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
DBV package
θJA
Package thermal impedance(3)
DCK package
DRL package
YZP package
Tstg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
206
252
142
132
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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 SN74AUC1G00
www.ti.com
Recommended Operating Conditions(1)
SN74AUC1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCES368O – SEPTEMBER 2001 – REVISED JANUARY 2007
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v
TA
Input transition rise or fall rate
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
MIN
0.8
VCC
0.65 × VCC
1.7
0
0
–40
MAX
2.7
0
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
10
85
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
II
A or B input
Ioff
ICC
Ci
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
IOH = –3 mA
IOH = –5 mA
IOH = –8 mA
IOH = –9 mA
IOL = 100 µA
IOL = 0.7 mA
IOL = 3 mA
IOL = 5 mA
IOL = 8 mA
IOL = 9 mA
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
IO = 0
VI = VCC or GND
VCC
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0 to 2.7 V
0
0.8 V to 2.7 V
2.5 V
(1) All typical values are at TA = 25°C.
MIN
VCC – 0.1
0.8
1
1.2
1.8
TYP (1)
0.55
0.25
3
MAX UNIT
V
0.2
0.3
V
0.4
0.45
0.6
±5 µA
±10 µA
10 µA
pF
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3



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