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Buffer Gate. SN74AUC1G126 Datasheet

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Buffer Gate. SN74AUC1G126 Datasheet






SN74AUC1G126 Gate. Datasheet pdf. Equivalent




SN74AUC1G126 Gate. Datasheet pdf. Equivalent





Part

SN74AUC1G126

Description

Single Bus Buffer Gate



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74AUC1G126 SCES383L – MARCH 2002 – REVISED JANUARY 2018 SN74AUC1 G126 Single Bus Buffer Gate With Tri-st ate Output 1 Features •1 Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G126 Datasheet


Texas Instruments SN74AUC1G126

SN74AUC1G126; -A) – 1000-V Charged-Device Model (C10 1) • Available in TI's NanoFree™ Pa ckage • Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support M ixed-Mode Signal Operation • Ioff Sup ports Partial Power Down Mode and Back Drive Protection • Sub-1 V Operable Maximum tpd of 2.5 ns at 1.8 V • L ow Power Consumption, 10-µA Maximum IC C • ±8-mA Output Drive at 1.8 V 2 A.


Texas Instruments SN74AUC1G126

pplications • AV Receiver • Audio Do ck: Portable • Blu-ray™ Player and Home Theater • Embedded PC • MP3 Pl ayer/Recorder (Portable Audio) • Pers onal Digital Assistant (PDA) • Power: AC/DC Supply, Single Controller • So lid State Drive (SSD): Client and Enter prise • TV: LCD, Digital, and High-De finition (HD) • Tablet: Enterprise Video Analytics: Server • Wireless Heads.


Texas Instruments SN74AUC1G126

et, Keyboard, and Mouse 3 Description T he SN74AUC1G126 bus buffer gate is oper ational at 0.8-V to 2.7-V VCC, but is d esigned specifically for 1.65-V to 1.95 -V VCC operation. The SN74AUC1G126 devi ce is a single line driver with a tri-s tate output. The output is disabled whe n the output-enable (OE) input is low. To ensure the high-impedance state duri ng power up or pow.

Part

SN74AUC1G126

Description

Single Bus Buffer Gate



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74AUC1G126 SCES383L – MARCH 2002 – REVISED JANUARY 2018 SN74AUC1 G126 Single Bus Buffer Gate With Tri-st ate Output 1 Features •1 Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G126 Datasheet




 SN74AUC1G126
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SN74AUC1G126
SCES383L – MARCH 2002 – REVISED JANUARY 2018
SN74AUC1G126 Single Bus Buffer Gate With Tri-state Output
1 Features
1 Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
• Available in TI's NanoFree™ Package
• Optimized for 1.8-V Operation and is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal Operation
• Ioff Supports Partial Power Down Mode and Back
Drive Protection
• Sub-1 V Operable
• Maximum tpd of 2.5 ns at 1.8 V
• Low Power Consumption, 10-µA Maximum ICC
• ±8-mA Output Drive at 1.8 V
2 Applications
• AV Receiver
• Audio Dock: Portable
• Blu-ray™ Player and Home Theater
• Embedded PC
• MP3 Player/Recorder (Portable Audio)
• Personal Digital Assistant (PDA)
• Power: AC/DC Supply, Single Controller
• Solid State Drive (SSD): Client and Enterprise
• TV: LCD, Digital, and High-Definition (HD)
• Tablet: Enterprise
• Video Analytics: Server
• Wireless Headset, Keyboard, and Mouse
3 Description
The SN74AUC1G126 bus buffer gate is operational
at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC1G126 device is a single line driver
with a tri-state output. The output is disabled when
the output-enable (OE) input is low.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
NanoFree™ package technology is a major
breakthrough in device packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, which prevents damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUC1G126DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74AUC1G126DCK SC70 (5)
2.00 mm × 1.25 mm
SN74AUC1G126YZP DSBGA (5) 1.388 mm × 0.888 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
OE
2
A
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.




 SN74AUC1G126
SN74AUC1G126
SCES383L – MARCH 2002 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics: CL = 15 pF ...................... 7
6.7 Switching Characteristics: CL = 30 pF ...................... 7
6.8 Operating Characteristics.......................................... 7
7 Typical Characteristics.......................................... 8
8 Parameter Measurement Information ................ 10
9 Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ................................................ 14
11 Power Supply Recommendations ..................... 15
12 Layout................................................................... 16
12.1 Layout Guidelines ................................................. 16
12.2 Layout Example .................................................... 16
13 Device and Documentation Support ................. 17
13.1 Documentation Support ........................................ 17
13.2 Receiving Notification of Documentation Updates 17
13.3 Community Resources.......................................... 17
13.4 Trademarks ........................................................... 17
13.5 Electrostatic Discharge Caution ............................ 17
13.6 Glossary ................................................................ 17
14 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (June 2017) to Revision L
Page
• Updated body size of YZP package. ..................................................................................................................................... 1
• Added junction temperature to Absolute Maximum Ratings .................................................................................................. 4
• Add Detailed Description, Application and Implementation, Power Supply Recommendations, and Layout sections ........ 12
Changes from Revision J (July 2007) to Revision K
Page
• Deleted DRY package throughout data sheet........................................................................................................................ 1
• Added Applications, Device Information table, ESD Ratings table, Thermal Information table, Feature Description
section, Device Functional Modes, Device and Documentation Support section, and Mechanical, Packaging, and
Orderable Information section ................................................................................................................................................ 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data
sheet ...................................................................................................................................................................................... 1
2
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Copyright © 2002–2018, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G126




 SN74AUC1G126
www.ti.com
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
OE
1
5
VCC
A
2
GND
3
4
Y
PIN
NAME
DBV, DCK
YZP
A
2
B1
GND
3
C1
OE
1
A1
VCC
5
A2
Y
4
C2
YZP Package
5-Pin DSBGA
Bottom View
1
2
C GND
Y
B
A
A
OE
VCC
Not to scale
Pin Functions
I/O
I
Logic input
Ground
I
Output enable
Positive supply
O
Output
SN74AUC1G126
SCES383L – MARCH 2002 – REVISED JANUARY 2018
DCK Package
5-Pin SC70
Top View
OE
1
5
VCC
A
2
GND
3
4Y
DESCRIPTION
Copyright © 2002–2018, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G126
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