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D-TYPE FLIP-FLOP. SN74AUC1G74 Datasheet

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D-TYPE FLIP-FLOP. SN74AUC1G74 Datasheet






SN74AUC1G74 FLIP-FLOP. Datasheet pdf. Equivalent




SN74AUC1G74 FLIP-FLOP. Datasheet pdf. Equivalent





Part

SN74AUC1G74

Description

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


www.ti.com SN74AUC1G74 SINGLE POSITIVE- EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CL EAR AND PRESET SCES537D – DECEMBER 20 03 – REVISED JUNE 2007 FEATURES • Available in the Texas Instruments Nan oFree™ Package • Optimized for 1.8- V Operation and Is 3.6-V I/O Tolerant t o Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mod e Operation • Sub-1-V Operable.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G74 Datasheet


Texas Instruments SN74AUC1G74

SN74AUC1G74; • Max tpd of 1.5 ns at 1.8 V DCT PAC KAGE (TOP VIEW) DCU PACKAGE (TOP VIEW) • Low Power Consumption, 10-μA Max ICC • ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protectio n Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Mod el (C101) RSE PACKAGE (TOP VIEW) Y.


Texas Instruments SN74AUC1G74

ZP OR YZT PACKAGE (BOTTOM VIEW) 7 CLK 6 D 5Q CLK 1 D 2 Q 3 GND 4 8 VC C CLK 1 D2 7 PRE Q3 6 CLR GND 4 5 Q 8 VCC 7 PRE 6 CLR 5Q VCC 8 4 GND GND 4 5 Q Q 3 6 CLR D 2 7 PR E CLK 1 8 VCC PRE 1 CLR 2 Q3 See me chanical drawings for dimensions. DESC RIPTION/ORDERING INFORMATION This singl e positive-edge-triggered D-type flip-f lop is operational.


Texas Instruments SN74AUC1G74

at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC o peration. A low level at the preset (PR E) or clear (CLR) input sets or resets the outputs, regardless of the levels o f the other inputs. When PRE and CLR ar e inactive (high), data at the data (D) input meeting the setup time requireme nts is transferred to the outputs on th e positive-going e.

Part

SN74AUC1G74

Description

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


www.ti.com SN74AUC1G74 SINGLE POSITIVE- EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CL EAR AND PRESET SCES537D – DECEMBER 20 03 – REVISED JUNE 2007 FEATURES • Available in the Texas Instruments Nan oFree™ Package • Optimized for 1.8- V Operation and Is 3.6-V I/O Tolerant t o Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mod e Operation • Sub-1-V Operable.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G74 Datasheet




 SN74AUC1G74
www.ti.com
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.5 ns at 1.8 V
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
Low Power Consumption, 10-μA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RSE PACKAGE
(TOP VIEW)
YZP OR YZT PACKAGE
(BOTTOM VIEW)
CLK
1
D
2
Q
3
GND
4
8
VCC
CLK 1
D2
7
PRE
Q3
6
CLR
GND
4
5
Q
8
VCC
7 PRE
6 CLR
5Q
VCC 8
4 GND
GND 4 5 Q
Q 3 6 CLR
D 2 7 PRE
CLK
1 8 VCC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated




 SN74AUC1G74
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
www.ti.com
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZT (Pb-free)
Reel of 3000
Reel of 3000
SN74AUC1G74YZPR
SN74AUC1G74YZTR
_ _ _UP_
QFN – RSE
Reel of 3000 SN74AUC1G74RSER
UP
SSOP – DCT
Reel of 3000 SN74AUC1G74DCTR
U74_ _ _
VSSOP – DCU
Reel of 3000 SN74AUC1G74DCUR
U74_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP/YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUTS
PRE
CLR
CLK
D
L
H
X
X
X
L
X
X
H
H
H
H
H
L
H
H
L
X
OUTPUTS
Q
Q
H
L
L
H
H
L
L
H
Q0
Q0
CLR 6
CLK 1
C
D2
TG
LOGIC DIAGRAM (POSITIVE LOGIC)
C
C
C
TG
C
TG
C
C
TG
3
Q
5
Q
C
C
C
PRE 7
A. Pin numbers shown are for the DCT, DCU, YZP, and YZT packages only.
2
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 SN74AUC1G74
www.ti.com
SN74AUC1G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES537D – DECEMBER 2003 – REVISED JUNE 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
DCT package
θJA
Package thermal impedance(3)
DCU package
RSE package
YZP/YZT package
Tstg Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
220
227
253
102
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
Δt/Δv Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V to 1.65 V(2)
VCC = 1.65 V to 2.3 V(3)
VCC = 2.3 V to 2.7 V(3)
MIN
0.8
VCC
0.65 × VCC
1.7
0
0
–40
MAX
2.7
0
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
20
20
85
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) The data was taken at CL = 15 pF, RL = 2 k(see Figure 1).
(3) The data was taken at CL = 30 pF, RL = 500 (see Figure 1).
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