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EXCLUSIVE-OR GATE. SN74AUC1G86 Datasheet

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EXCLUSIVE-OR GATE. SN74AUC1G86 Datasheet






SN74AUC1G86 GATE. Datasheet pdf. Equivalent




SN74AUC1G86 GATE. Datasheet pdf. Equivalent





Part

SN74AUC1G86

Description

SINGLE 2-INPUT EXCLUSIVE-OR GATE



Feature


www.ti.com SN74AUC1G86 SINGLE 2-INPUT E XCLUSIVE-OR GATE SCES389J – MARCH 200 2 – REVISED NOVEMBER 2007 FEATURES 1 •2 Available in the Texas Instrument s NanoFree™ Package • Optimized for 1.8-V Operation and Is 3.6-V I/O Toler ant to Support Mixed-Mode Signal Operat ion • Ioff Supports Partial Power-Dow n-Mode Operation • Sub-1-V Operable Max tpd of 2.5 ns at 1.8 V • L.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G86 Datasheet


Texas Instruments SN74AUC1G86

SN74AUC1G86; ow Power Consumption, 10-µA Max ICC • ±8-mA Output Drive at 1.8 V • Latch -Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceed s JESD 22 – 2000-V Human-Body Model ( A114-A) – 200-V Machine Model (A115-A ) – 1000-V Charged-Device Model (C101 ) DBV PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) A 1 B 2 5 VCC A 1 5 VCC.


Texas Instruments SN74AUC1G86

B 2 GND 3 4 Y B2 A 15 VCC GND 3 4Y GND 3 4 Y See mechanical drawi ngs for dimensions. DESCRIPTION/ORDERI NG INFORMATION This single 2-input excl usive-OR gate is operational at 0.8-V t o 2.7-V VCC, but is designed specifical ly for 1.65-V to 1.95-V VCC operation. The SN74AUC1G86 performs the Boolean fu nction Y = A ⊕ B or Y = AB + AB in po sitive logic. A comm.


Texas Instruments SN74AUC1G86

on application is as a true/complement e lement. If the input is low, the other input is reproduced in true form at the output. If the input is high, the sign al on the other input is reproduced inv erted at the output. NanoFree™ packag e technology is a major breakthrough in IC packaging concepts, using the die a s the package. This device is fully spe cified for partial-p.

Part

SN74AUC1G86

Description

SINGLE 2-INPUT EXCLUSIVE-OR GATE



Feature


www.ti.com SN74AUC1G86 SINGLE 2-INPUT E XCLUSIVE-OR GATE SCES389J – MARCH 200 2 – REVISED NOVEMBER 2007 FEATURES 1 •2 Available in the Texas Instrument s NanoFree™ Package • Optimized for 1.8-V Operation and Is 3.6-V I/O Toler ant to Support Mixed-Mode Signal Operat ion • Ioff Supports Partial Power-Dow n-Mode Operation • Sub-1-V Operable Max tpd of 2.5 ns at 1.8 V • L.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G86 Datasheet




 SN74AUC1G86
www.ti.com
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES389J – MARCH 2002 – REVISED NOVEMBER 2007
FEATURES
1
2 Available in the Texas Instruments NanoFree™
Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial Power-Down-Mode
Operation
Sub-1-V Operable
Max tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
A
1
B
2
5
VCC
A
1
5
VCC
B
2
GND 3 4 Y
B2
A 15
VCC
GND
3
4Y
GND
3
4
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC1G86 performs the Boolean function Y = A B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1) (2)
ORDERABLE PART NUMBER
NanoFree™
WCSP (DSBGA) – YZP (Pb-free)
Reel of 3000
SN74AUC1G86YZPR
SOT (SOT-23) – DBV
Reel of 3000 SN74AUC1G86DBVR
SOT (SC-70) – DCK
Reel of 3000 SN74AUC1G86DCKR
TOP-SIDE MARKING(3)
_ _ _UH_
U86_
UH_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2007, Texas Instruments Incorporated




 SN74AUC1G86
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES389J – MARCH 2002 – REVISED NOVEMBER 2007
www.ti.com
FUNCTION TABLE
INPUTS
A
B
L
L
L
H
H
L
H
H
OUTPUT
Y
L
H
H
L
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AUC1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
DBV package
θJA
Package thermal impedance(3)
DCK package
YZP package
Tstg Storage temperature range
MIN
MAX UNIT
–0.5
3.6 V
–0.5
3.6 V
–0.5
3.6 V
–0.5
VCC + 0.5 V
–50 mA
–50 mA
±20 mA
±100 mA
206
252 °C/W
154
–65
150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Copyright © 2002–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUC1G86




 SN74AUC1G86
www.ti.com
SN74AUC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES389J – MARCH 2002 – REVISED NOVEMBER 2007
RECOMMENDED OPERATING CONDITIONS(1)
VCC Supply voltage
VIH High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH High-level output current
IOL
Low-level output current
Δt/Δv Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
MIN
0.8
VCC
0.65 × VCC
1.7
0
0
–40
MAX UNIT
2.7 V
V
0
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
85
V
V
V
mA
mA
ns/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
II
A or B input
Ioff
ICC
Ci
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
IOH = –3 mA
IOH = –5 mA
IOH = –8 mA
IOH = –9 mA
IOL = 100 µA
IOL = 0.7 mA
IOL = 3 mA
IOL = 5 mA
IOL = 8 mA
IOL = 9 mA
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
IO = 0
VI = VCC or GND
VCC
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0 to 2.7 V
0
0.8 V to 2.7 V
2.5 V
(1) All typical values are at TA = 25°C.
MIN
VCC – 0.1
0.8
1
1.2
1.8
TYP (1)
0.55
0.25
2.5
MAX
0.2
0.3
0.4
0.45
0.6
±5
±10
10
UNIT
V
V
µA
µA
µA
pF
Copyright © 2002–2007, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN74AUC1G86



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