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BUS TRANSCEIVER. SN74AUC16245 Datasheet

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BUS TRANSCEIVER. SN74AUC16245 Datasheet






SN74AUC16245 TRANSCEIVER. Datasheet pdf. Equivalent




SN74AUC16245 TRANSCEIVER. Datasheet pdf. Equivalent





Part

SN74AUC16245

Description

16-BIT BUS TRANSCEIVER



Feature


SN74AUC16245 16ĆBIT BUS TRANSCEIVER WIT H 3ĆSTATE OUTPUTS SCES392E − MARCH 2 002 − REVISED DECEMBER 2002 D Member of the Texas Instruments Widebus Fa mily D Optimized for 1.8-V Operation an d is 3.6-V I/O Tolerant to Support Mixe d-Mode Signal Operation D Ioff Supports Partial-Power-Down Mode Operation D Su b 1-V Operable D Max tpd of 2 ns at 1.8 V D Low Power Consumption.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC16245 Datasheet


Texas Instruments SN74AUC16245

SN74AUC16245; , 20-µA Max ICC D ±8-mA Output Drive a t 1.8 V D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Prot ection Exceeds JESD 22 − 2000-V Human -Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Devic e Model (C101) description/ordering inf ormation This 16-bit (dual-octal) nonin verting bus transceiver is operational at 0.8-V to 2.7-V VCC, but.


Texas Instruments SN74AUC16245

is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC16245 is designed for asynchronous communicat ion between data buses. The control-fun ction implementation minimizes external timing requirements. DGG OR DGV PACKA GE (TOP VIEW) 1DIR 1 1B1 2 1B2 3 GND 4 1B3 5 1B4 6 VCC 7 1B5 8 1B6 9 GND 10 1 B7 11 1B8 12 2B1 13 2B2 14 GND 15 2B3 1 6 2B4 17 VCC 18 2B.


Texas Instruments SN74AUC16245

5 19 2B6 20 GND 21 2B7 22 2B8 23 2DIR 24 48 1OE 47 1A1 46 1A2 45 GND 44 1A3 43 1A4 42 VCC 41 1A5 40 1A6 39 GND 38 1A7 37 1A8 36 2A1 35 2A2 34 GND 33 2A3 32 2A4 31 VCC 30 2A5 29 2A6 28 GND 27 2A7 26 2A8 25 2OE This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmissi on from the A bus to the B bus or from the B bus to the A.

Part

SN74AUC16245

Description

16-BIT BUS TRANSCEIVER



Feature


SN74AUC16245 16ĆBIT BUS TRANSCEIVER WIT H 3ĆSTATE OUTPUTS SCES392E − MARCH 2 002 − REVISED DECEMBER 2002 D Member of the Texas Instruments Widebus Fa mily D Optimized for 1.8-V Operation an d is 3.6-V I/O Tolerant to Support Mixe d-Mode Signal Operation D Ioff Supports Partial-Power-Down Mode Operation D Su b 1-V Operable D Max tpd of 2 ns at 1.8 V D Low Power Consumption.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC16245 Datasheet




 SN74AUC16245
SN74AUC16245
16ĆBIT BUS TRANSCEIVER
WITH 3ĆSTATE OUTPUTS
SCES392E − MARCH 2002 − REVISED DECEMBER 2002
D Member of the Texas Instruments
WidebusFamily
D Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D Ioff Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max tpd of 2 ns at 1.8 V
D Low Power Consumption, 20-µA Max ICC
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit (dual-octal) noninverting bus
transceiver is operational at 0.8-V to 2.7-V VCC,
but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The SN74AUC16245 is designed for
asynchronous communication between data
buses. The control-function implementation
minimizes external timing requirements.
DGG OR DGV PACKAGE
(TOP VIEW)
1DIR 1
1B1 2
1B2 3
GND 4
1B3 5
1B4 6
VCC 7
1B5 8
1B6 9
GND 10
1B7 11
1B8 12
2B1 13
2B2 14
GND 15
2B3 16
2B4 17
VCC 18
2B5 19
2B6 20
GND 21
2B7 22
2B8 23
2DIR 24
48 1OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 VCC
41 1A5
40 1A6
39 GND
38 1A7
37 1A8
36 2A1
35 2A2
34 GND
33 2A3
32 2A4
31 VCC
30 2A5
29 2A6
28 GND
27 2A7
26 2A8
25 2OE
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP − DGG
Tape and reel SN74AUC16245DGGR AUC16245
−40°C to 85°C TVSOP − DGV
Tape and reel SN74AUC16245DGVR MH245
VFBGA − GQL
Tape and reel SN74AUC16245GQLR MH245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 SN74AUC16245
SN74AUC16245
16ĆBIT BUS TRANSCEIVER
WITH 3ĆSTATE OUTPUTS
SCES392E − MARCH 2002 − REVISED DECEMBER 2002
GQL PACKAGE
(TOP VIEW)
123456
A
B
C
D
E
F
G
H
J
K
terminal assignments
1
2
A
1DIR
NC
B
1B2
1B1
C
1B4
1B3
D
1B6
1B5
E
1B8
1B7
F
2B1
2B2
G
2B3
2B4
H
2B5
2B6
J
2B7
2B8
K
2DIR
NC
NC − No internal connection
3
NC
GND
VCC
GND
GND
VCC
GND
NC
logic diagram (positive logic)
1DIR 1
1A1 47
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE DIR
OPERATION
L
L
B data to A bus
L
H A data to B bus
H
X
Isolation
48
1OE
2 1B1
24
2DIR
36
2A1
4
NC
GND
VCC
GND
GND
VCC
GND
NC
5
6
NC
1OE
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A2
2A1
2A4
2A3
2A6
2A5
2A8
2A7
NC
2OE
25
2OE
13 2B1
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
To Seven Other Channels
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 SN74AUC16245
SN74AUC16245
16ĆBIT BUS TRANSCEIVER
WITH 3ĆSTATE OUTPUTS
SCES392E − MARCH 2002 − REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC Supply voltage
VIH High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
Active state
3-state
0.8
2.7
V
VCC
0.65 × VCC
V
1.7
0
0.35 × VCC V
0.7
0
3.6
V
0
VCC
V
0
3.6
IOH High-level output current
IOL
Low-level output current
t/v Input transition rise or fall rate
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
−0.7
−3
−5
mA
−8
−9
0.7
3
5
mA
8
9
5
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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