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D-TYPE LATCH. SN74AUC16373 Datasheet

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D-TYPE LATCH. SN74AUC16373 Datasheet






SN74AUC16373 LATCH. Datasheet pdf. Equivalent




SN74AUC16373 LATCH. Datasheet pdf. Equivalent





Part

SN74AUC16373

Description

16-BIT TRANSPARENT D-TYPE LATCH



Feature


www.ti.com FEATURES • Member of the Te xas Instruments Widebus™ Family • O ptimized for 1.8-V Operation and Is 3.6 -V I/O Tolerant to Support Mixed-Mode S ignal Operation • Ioff Supports Parti al-Power-Down Mode Operation • Sub-1- V Operable • Max tpd of 2 ns at 1.8 V • Low Power Consumption, 20-µA Max ICC • ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA .
Manufacture

Texas Instruments

Datasheet
Download SN74AUC16373 Datasheet


Texas Instruments SN74AUC16373

SN74AUC16373; Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Mode l (C101) DESCRIPTION/ORDERING INFORMATI ON This 16-bit transparent D-type latch is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC16 373 is particularly suitab.


Texas Instruments SN74AUC16373

le for implementing buffer registers, I/ O ports, bidirectional bus drivers, and working registers. The device can be u sed as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. SN74AUC16373 16-B IT TRANSPARENT D-T.


Texas Instruments SN74AUC16373

YPE LATCH WITH 3-STATE OUTPUTS SCES401C – JULY 2002 – REVISED JUNE 2005 DG G OR DGV PACKAGE (TOP VIEW) 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1 Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2OE 24 48 1LE 47 1D1 46 1D2 45 GND 44 1D3 43 1D4 42 VCC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 36 2D1 35 2D2 34 GND 3.

Part

SN74AUC16373

Description

16-BIT TRANSPARENT D-TYPE LATCH



Feature


www.ti.com FEATURES • Member of the Te xas Instruments Widebus™ Family • O ptimized for 1.8-V Operation and Is 3.6 -V I/O Tolerant to Support Mixed-Mode S ignal Operation • Ioff Supports Parti al-Power-Down Mode Operation • Sub-1- V Operable • Max tpd of 2 ns at 1.8 V • Low Power Consumption, 20-µA Max ICC • ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA .
Manufacture

Texas Instruments

Datasheet
Download SN74AUC16373 Datasheet




 SN74AUC16373
www.ti.com
FEATURES
Member of the Texas Instruments Widebus™
Family
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 2 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 16-bit transparent D-type latch is operational at
0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC16373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. The device can be
used as two 8-bit latches or one 16-bit latch. When
the latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D
inputs.
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED JUNE 2005
DGG OR DGV PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
VCC 7
1Q5 8
1Q6 9
GND 10
1Q7 11
1Q8 12
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
VCC 18
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
48 1LE
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 VCC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 VCC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2LE
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
TSSOP - DGG
Tape and reel
SN74AUC16373DGGR
TVSOP - DGV
Tape and reel
SN74AUC16373DGVR
VFBGA - GQL
Tape and reel
SN74AUC16373GQLR
TOP-SIDE MARKING
AUC16373
MH373
MH373
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated




 SN74AUC16373
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED JUNE 2005
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
12 3 4 5 6
A
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS(1)
1
2
3
4
5
6
A 1OE
NC
NC
NC
NC
1LE
B 1Q2
1Q1 GND
GND
1D1
1D2
C 1Q4
1Q3
VCC
VCC
1D3 1D4
D 1Q6
1Q5 GND
GND
1D5
1D6
E 1Q8 1Q7
1D7 1D8
F 2Q1 2Q2
2D2 2D1
G 2Q3
2Q4 GND
GND
2D4
2D3
H 2Q5
2Q6
VCC
VCC
2D6 2D5
J
2Q7
2Q8 GND
GND
2D8
2D7
K 2OE
NC
NC
NC
NC
2LE
(1) NC - No internal connection
FUNCTION TABLE
(EACH LATCH)
INPUTS
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
OUTPUT
Q
H
L
Q0
Z
1
1OE
48
1LE
1D1 47
LOGIC DIAGRAM (POSITIVE LOGIC)
24
2OE
25
2LE
C1
2
C1
1D
1Q1 2D1 36
1D
13
2Q1
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
To Seven Other Channels
2




 SN74AUC16373
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
SN74AUC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES401C – JULY 2002 – REVISED JUNE 2005
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
DGG package
θJA
Package thermal impedance(3)
DGV package
GQL package
Tstg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
70
58
42
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v
TA
Input transition rise or fall rate
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
MIN
0.8
VCC
0.65 × VCC
1.7
0
0
–40
MAX
2.7
0
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
85
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3



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