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D-TYPE FLIP-FLOP. SN74AUC16374 Datasheet

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D-TYPE FLIP-FLOP. SN74AUC16374 Datasheet






SN74AUC16374 FLIP-FLOP. Datasheet pdf. Equivalent




SN74AUC16374 FLIP-FLOP. Datasheet pdf. Equivalent





Part

SN74AUC16374

Description

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


www.ti.com FEATURES • Member of the Te xas Instruments Widebus™ Family • O ptimized for 1.8-V Operation and Is 3.6 -V I/O Tolerant to Support Mixed-Mode S ignal Operation • Ioff Supports Parti al-Power-Down Mode Operation • Sub-1- V Operable • Max tpd of 2.8 ns at 1.8 V • Low Power Consumption, 20-µA Ma x ICC • ±8-mA Output Drive at 1.8 V • Latch-Up Performance Exceeds 100 m.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC16374 Datasheet


Texas Instruments SN74AUC16374

SN74AUC16374; A Per JESD 78, Class II • ESD Protecti on Exceeds JESD 22 – 2000-V Human-Bod y Model (A114-A) – 200-V Machine Mode l (A115-A) – 1000-V Charged-Device Mo del (C101) DESCRIPTION/ORDERING INFORMA TION This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2. 7-V VCC, but is designed specifically f or 1.65-V to 1.95-V VCC operation. The SN74AUC16374 is particular.


Texas Instruments SN74AUC16374

ly suitable for implementing buffer regi sters, I/O ports, bidirectional bus dri vers, and working registers. It can be used as two 8-bit flip-flops or one 16- bit flip-flop. On the positive transiti on of the clock (CLK) input, the Q outp uts of the flip-flop take on the logic levels set up at the data (D) inputs. SN74AUC16374 16-BIT EDGE-TRIGGERED D-TY PE FLIP-FLOP WITH .


Texas Instruments SN74AUC16374

3-STATE OUTPUTS SCES403E – JULY 2002 REVISED APRIL 2007 DGG OR DGV PACKA GE (TOP VIEW) 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 GND 10 1Q 7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2OE 24 48 1CLK 47 1D1 46 1D 2 45 GND 44 1D3 43 1D4 42 VCC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 36 2D1 35 2D2 34 GND 33 2D3 32 2D4 .

Part

SN74AUC16374

Description

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


www.ti.com FEATURES • Member of the Te xas Instruments Widebus™ Family • O ptimized for 1.8-V Operation and Is 3.6 -V I/O Tolerant to Support Mixed-Mode S ignal Operation • Ioff Supports Parti al-Power-Down Mode Operation • Sub-1- V Operable • Max tpd of 2.8 ns at 1.8 V • Low Power Consumption, 20-µA Ma x ICC • ±8-mA Output Drive at 1.8 V • Latch-Up Performance Exceeds 100 m.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC16374 Datasheet




 SN74AUC16374
www.ti.com
FEATURES
Member of the Texas Instruments Widebus™
Family
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 2.8 ns at 1.8 V
Low Power Consumption, 20-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING
INFORMATION
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC16374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. It can be used as
two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403E – JULY 2002 – REVISED APRIL 2007
DGG OR DGV PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
VCC 7
1Q5 8
1Q6 9
GND 10
1Q7 11
1Q8 12
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
VCC 18
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
48 1CLK
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 VCC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 VCC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2CLK
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1) (2)
ORDERABLE PART NUMBER
TSSOP – DGG
Reel of 2000
SN74AUC16374DGGR
TVSOP – DGV
Reel of 2000
SN74AUC16374DGVR
VFBGA – ZQL
Reel of 1000
SN74AUC16374ZQLR
TOP-SIDE MARKING
AUC16374
MH374
MH374
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2007, Texas Instruments Incorporated




 SN74AUC16374
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403E – JULY 2002 – REVISED APRIL 2007
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
12 3 4 5 6
A
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS(1)
1
A 1OE
B 1Q2
C 1Q4
D 1Q6
E 1Q8
F 2Q1
G 2Q3
H 2Q5
J 2Q7
K 2OE
2
3
4
5
6
NC
NC
NC
NC 1CLK
1Q1
GND GND
1D1
1D2
1Q3
VCC
VCC
1D3
1D4
1Q5
GND GND
1D5
1D6
1Q7
1D7
1D8
2Q2
2D2
2D1
2Q4
GND GND
2D4
2D3
2Q6
VCC
VCC
2D6
2D5
2Q8
GND GND
2D8
2D7
NC
NC
NC
NC 2CLK
(1) NC - No internal connection
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OE CLK
D
L
H
L
L
L H or L X
H
X
X
OUTPUT
Q
H
L
Q0
Z
1
1OE
1CLK 48
47
1D1
LOGIC DIAGRAM (POSITIVE LOGIC)
2OE 24
C1
1D
2CLK 25
2
1Q1
36
2D1
C1
1D
13
2Q1
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
To Seven Other Channels
2
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 SN74AUC16374
www.ti.com
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403E – JULY 2002 – REVISED APRIL 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
DGG package
θJA
Package thermal impedance(3)
DGV package
GQL package
Tstg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
70
58
42
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v
TA
Input transition rise or fall rate
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
MIN
0.8
VCC
0.65 × VCC
1.7
0
0
–40
MAX
2.7
0
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
85
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3



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