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POSITIVE-AND GATE. SN74AUC08 Datasheet

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POSITIVE-AND GATE. SN74AUC08 Datasheet






SN74AUC08 GATE. Datasheet pdf. Equivalent




SN74AUC08 GATE. Datasheet pdf. Equivalent





Part

SN74AUC08

Description

QUADRUPLE 2-INPUT POSITIVE-AND GATE



Feature


www.ti.com FEATURES • Optimized for 1. 8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down M ode Operation • Sub-1-V Operable • Max tpd of 1.9 ns at 1.8 V • Low Powe r Consumption, 10-µA Max ICC • ±8-m A Output Drive at 1.8 V • Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds J.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC08 Datasheet


Texas Instruments SN74AUC08

SN74AUC08; ESD 22 – 2000-V Human-Body Model (A114 -A) – 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) G ND 3Y SN74AUC08 QUADRUPLE 2-INPUT POSI TIVE-AND GATE SCES512A – NOVEMBER 200 3 – REVISED MARCH 2005 RGY PACKAGE (T OP VIEW) 1A VCC 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 7 14 13 4B 12 4A 11 4Y 10 3B 9 3 A 8 DESCRIPTION/ORDERING INFORMATION T his quadruple 2-input positi.


Texas Instruments SN74AUC08

ve-AND gate is operational at 0.8-V to 2 .7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC08 device performs the Boolean function Y + A • B or Y + A ) B in po sitive logic. This device is fully spec ified for partial-power-down applicatio ns using Ioff. The Ioff circuitry disab les the outputs, preventing damaging cu rrent backflow throu.


Texas Instruments SN74AUC08

gh the device when it is powered down. TA –40°C to 85°C QFN – RGY ORDE RING INFORMATION PACKAGE (1) ORDERABL E PART NUMBER Tape and reel SN74AUC08 RGYR TOP-SIDE MARKING MS08 (1) Packag e drawings, standard packing quantities , thermal data, symbolization, and PCB design guidelines are available at www. ti.com/sc/package. FUNCTION TABLE (EAC H GATE) INPUTS A B H.

Part

SN74AUC08

Description

QUADRUPLE 2-INPUT POSITIVE-AND GATE



Feature


www.ti.com FEATURES • Optimized for 1. 8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down M ode Operation • Sub-1-V Operable • Max tpd of 1.9 ns at 1.8 V • Low Powe r Consumption, 10-µA Max ICC • ±8-m A Output Drive at 1.8 V • Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds J.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC08 Datasheet




 SN74AUC08
www.ti.com
FEATURES
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.9 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN74AUC08
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES512A – NOVEMBER 2003 – REVISED MARCH 2005
RGY PACKAGE
(TOP VIEW)
1
1B 2
1Y 3
2A 4
2B 5
2Y 6
7
14
13 4B
12 4A
11 4Y
10 3B
9 3A
8
DESCRIPTION/ORDERING INFORMATION
This quadruple 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC08 device performs the Boolean function Y + A B or Y + A ) B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
QFN – RGY
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
Tape and reel
SN74AUC08RGYR
TOP-SIDE MARKING
MS08
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH GATE)
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
H
L
L
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
Y
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated




 SN74AUC08
SN74AUC08
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES512A – NOVEMBER 2003 – REVISED MARCH 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
www.ti.com
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance(3)
Tstg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
47
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V to 1.65 V(2)
VCC = 1.65 V to 1.95 V(3)
VCC = 2.3 V to 2.7 V(3)
MIN
0.8
VCC
0.65 × VCC
1.7
0
0
–40
MAX
2.7
0
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
15
5
85
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) The data was taken at CL = 15 pF, RL = 2 k(see Figure 1).
(3) The data was taken at CL = 30 pF, RL = 500 (see Figure 1).
2




 SN74AUC08
www.ti.com
SN74AUC08
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES512A – NOVEMBER 2003 – REVISED MARCH 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
VOH
IOH = –3 mA
IOH = –5 mA
IOH = –8 mA
IOH = –9 mA
IOL = 100 µA
IOL = 0.7 mA
VOL
IOL = 3 mA
IOL = 5 mA
IOL = 8 mA
IOL = 9 mA
II
A or B inputs VI = VCC or GND
Ioff
VI or VO = 2.7 V
ICC
VI = VCC or GND,
IO = 0
Ci
VI = VCC or GND
VCC
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0 to 2.7 V
0
0.8 V to 2.7 V
2.5 V
MIN
VCC – 0.1
0.8
1
1.2
1.8
TYP (1)
0.55
0.25
2
MAX
0.2
0.3
0.4
0.45
0.6
±5
±10
10
UNIT
V
V
µA
µA
µA
pF
(1) All typical values are at TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
VCC = 1.2 V VCC = 1.5 V
± 0.1 V
± 0.1 V
MIN MAX MIN MAX
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN TYP MAX MIN MAX
tpd
A or B
Y
5.4
0.9 3.4 0.6 2.3 0.4
1 1.9 0.3 1.3
UNIT
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN TYP MAX MIN MAX
tpd
A or B
Y
0.7 1.5 2.3 0.5 1.8
UNIT
ns
Operating Characteristics
TA = 25°C
PARAMETER
TEST
CONDITIONS
Cpd
Power dissipation
capacitance
f = 10 MHz
VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
14
14
14
14
17
UNIT
pF
3



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