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BUFFER GATE. SN74AUC34 Datasheet

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BUFFER GATE. SN74AUC34 Datasheet






SN74AUC34 GATE. Datasheet pdf. Equivalent




SN74AUC34 GATE. Datasheet pdf. Equivalent





Part

SN74AUC34

Description

HEX BUFFER GATE



Feature


www.ti.com FEATURES • Optimized for 1. 8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down M ode Operation • Sub-1-V Operable • Max tpd of 1.8 ns at 1.8 V • Low Powe r Consumption, 10-µA Max ICC • ±8-m A Output Drive at 1.8 V • Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds J.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC34 Datasheet


Texas Instruments SN74AUC34

SN74AUC34; ESD 22 – 2000-V Human-Body Model (A114 -A) – 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) G ND 4Y SN74AUC34 HEX BUFFER GATE SCES47 4 – AUGUST 2003 – REVISED OCTOBER 2 005 RGY PACKAGE (TOP VIEW) 1A VCC 1 1 Y 2 2A 3 2Y 4 3A 5 3Y 6 7 14 13 6A 12 6Y 11 5A 10 5Y 9 4A 8 DESCRIPTION/ORDE RING INFORMATION This hex buffer gate i s operational at 0.8-V to 2..


Texas Instruments SN74AUC34

7-V VCC, but is designed specifically fo r 1.65-V to 1.95-V VCC operation. The S N74AUC34 performs the Boolean function Y = A. This device is fully specified f or partial-power-down applications usin g Ioff. The Ioff circuitry disables the outputs, preventing damaging current b ackflow through the device when it is p owered down. ORDERING INFORMATION TA –40°C to 85°C QFN.


Texas Instruments SN74AUC34

– RGY PACKAGE (1) Tape and reel ORD ERABLE PART NUMBER SN74AUC34RGYR TOP-S IDE MARKING MS34 (1) Package drawings, standard packing quantities, thermal d ata, symbolization, and PCB design guid elines are available at www.ti.com/sc/p ackage. FUNCTION TABLE (EACH GATE) IN PUT A H L OUTPUT Y H L LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) A Y Plea se be aware that an .

Part

SN74AUC34

Description

HEX BUFFER GATE



Feature


www.ti.com FEATURES • Optimized for 1. 8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down M ode Operation • Sub-1-V Operable • Max tpd of 1.8 ns at 1.8 V • Low Powe r Consumption, 10-µA Max ICC • ±8-m A Output Drive at 1.8 V • Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds J.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC34 Datasheet




 SN74AUC34
www.ti.com
FEATURES
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.8 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN74AUC34
HEX BUFFER GATE
SCES474 – AUGUST 2003 – REVISED OCTOBER 2005
RGY PACKAGE
(TOP VIEW)
1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
7
14
13 6A
12 6Y
11 5A
10 5Y
9 4A
8
DESCRIPTION/ORDERING INFORMATION
This hex buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC34 performs the Boolean function Y = A.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–40°C to 85°C
QFN – RGY
PACKAGE (1)
Tape and reel
ORDERABLE PART NUMBER
SN74AUC34RGYR
TOP-SIDE MARKING
MS34
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH GATE)
INPUT
A
H
L
OUTPUT
Y
H
L
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated




 SN74AUC34
SN74AUC34
HEX BUFFER GATE
SCES474 – AUGUST 2003 – REVISED OCTOBER 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
www.ti.com
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance(3)
Tstg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
47
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v
TA
Input transition rise or fall rate
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V to 1.95 V
VCC = 2.3 V to 2.7 V
MIN
0.8
VCC
0.65 × VCC
1.7
0
0
–40
MAX
2.7
0
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
10
85
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2




 SN74AUC34
www.ti.com
SN74AUC34
HEX BUFFER GATE
SCES474 – AUGUST 2003 – REVISED OCTOBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
II
A inputs
Ioff
ICC
Ci
IOH = –100 µA
IOH = –0.7 mA
IOH = –3 mA
IOH = –5 mA
IOH = –8 mA
IOH = –9 mA
IOL = 100 µA
IOL = 0.7 mA
IOL = 3 mA
IOL = 5 mA
IOL = 8 mA
IOL = 9 mA
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
(1) All typical values are at TA = 25°C.
VCC
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0 to 2.7 V
0
0.8 V to 2.7 V
2.5 V
MIN TYP(1) MAX
VCC – 0.1
0.55
0.8
1
1.2
1.8
0.2
0.25
0.3
0.4
0.45
0.6
±5
±10
10
2
UNIT
V
V
µA
µA
µA
pF
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
VCC = 1.2 V VCC = 1.5 V
± 0.1 V
± 0.1 V
MIN MAX MIN MAX
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN TYP MAX MIN MAX
tpd
A
Y
5.6
0.9 3.7 0.9 2.5 0.6 0.9 1.8 0.5 1.4
UNIT
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN TYP MAX MIN MAX
tpd
A
Y
0.9 1.4 2.4 0.9 1.8
UNIT
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V
TYP
TYP
TYP
TYP
16
17
17
17
VCC = 2.5 V
TYP
19
UNIT
pF
3



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