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D-TYPE FLIP-FLOP. SN74AUC74 Datasheet

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D-TYPE FLIP-FLOP. SN74AUC74 Datasheet






SN74AUC74 FLIP-FLOP. Datasheet pdf. Equivalent




SN74AUC74 FLIP-FLOP. Datasheet pdf. Equivalent





Part

SN74AUC74

Description

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


www.ti.com SN74AUC74 DUAL POSITIVE-EDGE -TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES483A – AUGUST 2003 – REVISED MARCH 2005 FEATURES • Optim ized for 1.8-V Operation and Is 3.6-V I /O Tolerant to Support Mixed-Mode Signa l Operation • Ioff Supports Partial-P ower-Down Mode Operation • Sub-1-V Op erable • Max tpd of 1.8 ns at 1.8 V Low Power Consumption, 10-µA .
Manufacture

Texas Instruments

Datasheet
Download SN74AUC74 Datasheet


Texas Instruments SN74AUC74

SN74AUC74; Max ICC • ±8-mA Output Drive at 1.8 V • Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II • ESD Protect ion Exceeds JESD 22 – 2000-V Human-Bo dy Model (A114-A) – 200-V Machine Mod el (A115-A) – 1000-V Charged-Device M odel (C101) GND 2Q RGY PACKAGE (TOP V IEW) 1CLR VCC 1 1D 2 1CLK 3 1PRE 4 1Q 5 1Q 6 7 14 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 DESCRIPTION/ORDERI.


Texas Instruments SN74AUC74

NG INFORMATION This dual positive-edge-t riggered D-type flip-flop is operationa l at 0.8-V to 2.7-V VCC, but is designe d specifically for 1.65-V to 1.95-V VCC operation. A low level at the preset ( PRE) or clear (CLR) inputs sets or rese ts the outputs, regardless of the level s of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting .


Texas Instruments SN74AUC74

the setup time requirements is transferr ed to the outputs on the positive-going edge of the clock pulse. Clock trigger ing occurs at a voltage level and is no t directly related to the rise time of the clock pulse. Following the hold-tim e interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the fl ip-flop for higher.

Part

SN74AUC74

Description

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP



Feature


www.ti.com SN74AUC74 DUAL POSITIVE-EDGE -TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES483A – AUGUST 2003 – REVISED MARCH 2005 FEATURES • Optim ized for 1.8-V Operation and Is 3.6-V I /O Tolerant to Support Mixed-Mode Signa l Operation • Ioff Supports Partial-P ower-Down Mode Operation • Sub-1-V Op erable • Max tpd of 1.8 ns at 1.8 V Low Power Consumption, 10-µA .
Manufacture

Texas Instruments

Datasheet
Download SN74AUC74 Datasheet




 SN74AUC74
www.ti.com
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES483A – AUGUST 2003 – REVISED MARCH 2005
FEATURES
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.8 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RGY PACKAGE
(TOP VIEW)
1
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
7
14
13 2CLR
12 2D
11 2CLK
10 2PRE
9 2Q
8
DESCRIPTION/ORDERING INFORMATION
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically
for 1.65-V to 1.95-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–40°C to 85°C
QFN – RGY
PACKAGE (1)
Tape and reel
ORDERABLE PART NUMBER
SN74AUC74RGYR
TOP-SIDE MARKING
MS74
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
PRE
CLR
CLK
D
L
H
X
X
X
L
X
X
H
H
H
H
H
L
H
H
L
X
OUTPUTS
Q
Q
H
L
L
H
H
L
L
H
Q0
Q0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated




 SN74AUC74
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES483A – AUGUST 2003 – REVISED MARCH 2005
LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC)
PRE
CLK
C
C
C
TG
C
C
D
TG
TG
C
C
TG
www.ti.com
Q
Q
C
C
C
CLR
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Output voltage range(2)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
θJA
Package thermal impedance(3)
Tstg
Storage temperature range
MIN
MAX
–0.5
3.6
–0.5
3.6
–0.5
3.6
–0.5 VCC + 0.5
–50
–50
±20
±100
47
–65
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.
2




 SN74AUC74
www.ti.com
Recommended Operating Conditions(1)
SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES483A – AUGUST 2003 – REVISED MARCH 2005
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
t/v
TA
Input transition rise or fall rate
Operating free-air temperature
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
MIN
0.8
VCC
0.65 × VCC
1.7
0
0
–40
MAX
2.7
0
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
5
8
9
20
85
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
II
Ioff
ICC
D inputs
Ci
Control inputs
TEST CONDITIONS
IOH = –100 µA
IOH = –0.7 mA
IOH = –3 mA
IOH = –5 mA
IOH = –8 mA
IOH = –9 mA
IOL = 100 µA
IOL = 0.7 mA
IOL = 3 mA
IOL = 5 mA
IOL = 8 mA
IOL = 9 mA
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
IO = 0
VI = VCC or GND
VI = VCC or GND
VCC
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V to 2.7 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0 to 2.7 V
0
0.8 V to 2.7 V
2.5 V
2.5 V
(1) All typical values are at TA = 25°C.
MIN
VCC – 0.1
0.8
1
1.2
1.8
TYP(1) MAX UNIT
0.55
V
0.2
0.25
0.3
V
0.4
0.45
0.6
±5 µA
±10 µA
10 µA
2
pF
2.5
3



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