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eFuse. TPS25940A Datasheet

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eFuse. TPS25940A Datasheet






TPS25940A eFuse. Datasheet pdf. Equivalent




TPS25940A eFuse. Datasheet pdf. Equivalent





Part

TPS25940A

Description

eFuse



Feature


Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPS25940A, TPS25940L SLVSCF3 A – JUNE 2014 – REVISED MARCH 2015 TPS25940x 2.7 – 18V eFuse with True R everse Blocking and DevSleep Support fo r SSDs 1 Features •1 2.7 V – 18 V Operating Voltage, 20 V (Max) • 42 m RON (Typical) • 0.6 A to 5.3 A Adju stable Current Limit (±8%) • IMON.
Manufacture

Texas Instruments

Datasheet
Download TPS25940A Datasheet


Texas Instruments TPS25940A

TPS25940A; Current Indicator Output (±8%) • 200 μA Operating IQ (Typical) • 95 μA DevSleep Mode IQ (Typical) • 15 μA D isabled IQ (Typical) • ±2% Overvolta ge, Undervoltage Threshold • Reverse Current Blocking • 1 μs Reverse Volt age Shutoff • Programmable dVo/dt Con trol • Power Good and Fault Outputs -40°C to 125°C Junction Temperatur e Range • UL 2367 Recognized – File No. 1699.


Texas Instruments TPS25940A

10 – RILIM ≥ 20 kΩ (4.81 A max) • UL60950 - Safe during Single Point Fai lure Test – Open/Short ILIM detection 2 Applications • PCIe/SATA/SAS HDD a nd SSD Drives • Enterprise and Micro Servers • Smart Load Switch • Set-T op-Box (STB), DTVs and Game Consoles RAID Cards - Holdup Power Management • Telecom Switches and Routers • Ad apter Powered Devices 3 Description The .


Texas Instruments TPS25940A

TPS25940 eFuse Power Switch is a compact , feature rich power management device with a full suite of protection functio ns, including a low power DevSleep™ m ode that supports compliance with the S ATA™ Device Sleep standard. The wide operating range allows control of many popular DC bus voltages. Integrated bac k to back FETs provide bidirectional cu rrent control making t.

Part

TPS25940A

Description

eFuse



Feature


Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPS25940A, TPS25940L SLVSCF3 A – JUNE 2014 – REVISED MARCH 2015 TPS25940x 2.7 – 18V eFuse with True R everse Blocking and DevSleep Support fo r SSDs 1 Features •1 2.7 V – 18 V Operating Voltage, 20 V (Max) • 42 m RON (Typical) • 0.6 A to 5.3 A Adju stable Current Limit (±8%) • IMON.
Manufacture

Texas Instruments

Datasheet
Download TPS25940A Datasheet




 TPS25940A
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TPS25940A, TPS25940L
SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
TPS25940x 2.7 – 18V eFuse with True Reverse Blocking and DevSleep Support for SSDs
1 Features
1 2.7 V – 18 V Operating Voltage, 20 V (Max)
• 42 mΩ RON (Typical)
• 0.6 A to 5.3 A Adjustable Current Limit (±8%)
• IMON Current Indicator Output (±8%)
• 200 μA Operating IQ (Typical)
• 95 μA DevSleep Mode IQ (Typical)
• 15 μA Disabled IQ (Typical)
• ±2% Overvoltage, Undervoltage Threshold
• Reverse Current Blocking
• 1 μs Reverse Voltage Shutoff
• Programmable dVo/dt Control
• Power Good and Fault Outputs
• -40°C to 125°C Junction Temperature Range
• UL 2367 Recognized
– File No. 169910
– RILIM 20 kΩ (4.81 A max)
• UL60950 - Safe during Single Point Failure Test
– Open/Short ILIM detection
2 Applications
• PCIe/SATA/SAS HDD and SSD Drives
• Enterprise and Micro Servers
• Smart Load Switch
• Set-Top-Box (STB), DTVs and Game Consoles
• RAID Cards - Holdup Power Management
• Telecom Switches and Routers
• Adapter Powered Devices
3 Description
The TPS25940 eFuse Power Switch is a compact,
feature rich power management device with a full
suite of protection functions, including a low power
DevSleep™ mode that supports compliance with the
SATA™ Device Sleep standard. The wide operating
range allows control of many popular DC bus
voltages. Integrated back to back FETs provide
bidirectional current control making the device well
suited for systems with load side holdup energy that
must not drain back to a failed supply bus.
Load, source and device protection are provided with
many programmable features including overcurrent,
dVo/dt ramp and overvoltage, undervoltage
thresholds. For system status monitoring and
downstream load control, the device provides
PGOOD, FLT and precise current monitor output.
Precise programmable undervoltage, overvoltage
thresholds and the low IQ DevSleep mode simplify
SSD power management design.
The TPS25940 monitors V(IN) and V(OUT) to provide
true reverse current blocking when V(IN) < (V(OUT) - 10
mV). This function supports swift changeover to a
boosted voltage energy storage element in systems
where backup voltage is greater than bus voltage.
Device Information(1)
PART NUMBER(2)
PACKAGE
BODY SIZE (NOM)
TPS25940A
TPS25940L
WQFN (20)
3.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) TPS25940L = Latched, TPS25940A = Auto Retry
4 Simplified Schematic
2.7 to 18 V
V(IN)
IN
RTOTAL =
EN/UVLO 42 m:
OUT
FLT
OVP
PGOOD
DEVSLP
PGTH
dVdT
IMON
GND
ILIM
TPS25940x
To Load
Power Fail Detection and Blocking
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




 TPS25940A
TPS25940A, TPS25940L
SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Characteristics ............................................ 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements ................................................ 7
7.7 Typical Characteristics .............................................. 8
8 Parametric Measurement Information ............... 15
9 Detailed Description ............................................ 16
9.1 Overview ................................................................. 16
9.2 Functional Block Diagram ....................................... 17
9.3 Feature Description................................................. 18
9.4 Device Functional Modes........................................ 22
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Application ................................................ 24
10.3 System Examples ................................................. 32
11 Power Supply Recommendations ..................... 35
11.1 Transient Protection .............................................. 35
11.2 Output Short-Circuit Measurements ..................... 36
12 Layout................................................................... 37
12.1 Layout Guidelines ................................................. 37
12.2 Layout Example .................................................... 38
13 Device and Documentation Support ................. 39
13.1 Related Links ........................................................ 39
13.2 Trademarks ........................................................... 39
13.3 Electrostatic Discharge Caution ............................ 39
13.4 Glossary ................................................................ 39
14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
5 Revision History
Changes from Original (June 2014) to Revision A
Page
• Changed Features From: UL2367 Recognition Pending To: UL 2367 Recognized, RILIM 20 kΩ (4.81 A max), File
No. 169910 ............................................................................................................................................................................. 1
• Moved the Storage Temperature From the Handling Ratings table To Absolute Maximum Ratings table .......................... 4
• Changed the Handling Ratings table To: ESD Ratings table ................................................................................................ 4
• Added Test Condition to I(LIM): "R(ILIM) = 20 kΩ" in the Electrical Characteristics .................................................................. 5
• Changed Figure 24............................................................................................................................................................... 10
• Added condition R(ILIM) = 17.8 kΩ to Figure 40 and Figure 41 ............................................................................................ 13
• Changed Figure 43 .............................................................................................................................................................. 17
• Changed Equation 6 to include I(IMON_OS).............................................................................................................................. 21
• Added the NOTE to Application and Implementation .......................................................................................................... 24
• Added Note to Figure 57 ..................................................................................................................................................... 28
• Changed Equation 35 From: V(IN) x I(LOAD) To: V(IN) + I(LOAD)................................................................................................. 35
2
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Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS25940A TPS25940L




 TPS25940A
www.ti.com
6 Pin Configuration and Functions
TPS25940
RVC PACKAGE
(TOP VIEW)
TPS25940A, TPS25940L
SLVSCF3A – JUNE 2014 – REVISED MARCH 2015
DEVSLP 1
PGOOD 2
PGTH 3
OUT 4
OUT 5
OUT 6
Thermal
Pad
16 GND
15 OVP
14 EN
13 IN
12 IN
11 IN
NAME
DEVSLP
PGOOD
PGTH
OUT
IN
EN/UVLO
NO.
1
2
3
4-8
9 - 13
14
OVP
15
GND
16
ILIM
17
dVdT
18
IMON
19
FLT
20
PowerPADTM
Pin Functions
I/O
DESCRIPTION
I
Active High. DevSleep Mode control. A high at this pin will activate the DevSleep mode(Low Power Mode).
O Active High. A high indicates PGTH has crossed the threshold value. It is an open drain output.
I
Positive input of PGOOD comparator.
O Power Output of the device.
I
Power Input and supply voltage of the device.
I
Input for setting programmable undervoltage lockout threshold. An undervoltage event will open internal FET and assert
FLT to indicate power-failure. When pulled to GND, resets the fault latch in TPS25940L.
I
Input for setting programmable overvoltage protection threshold. An overvoltage event will open the internal FET and
assert FLT to indicate overvoltage.
— Ground.
I/O A resistor from this pin to GND sets the overload and short-circuit current limit.
I/O A capacitor from this pin to GND sets the ramp rate of output voltage.
O
This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to GND converts current
to proportional voltage, used as analog current monitor.
O
Fault event indicator, goes low to indicate fault condition due to Undervoltage, Overvoltage, Reverse voltage and Thermal
shutdown event. It is an open drain output.
The GND terminal must be connected to the exposed PowerPAD. This PowerPAD must be connected to a PCB ground
plane using multiple vias for good thermal performance.
Copyright © 2014–2015, Texas Instruments Incorporated
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3
Product Folder Links: TPS25940A TPS25940L



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