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PSoC-62 MCU. CY8C624A Datasheet

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PSoC-62 MCU. CY8C624A Datasheet
















CY8C624A MCU. Datasheet pdf. Equivalent













Part

CY8C624A

Description

PSoC-62 MCU



Feature


PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet PSoC 62 MCU General Description PSoC ® 6 MCU is a high-performance, ultra-l ow-power and secured MCU platform, purp ose-built for IoT applications. The CY8 C62x8/A product line, based on the PSoC 6 MCU platform, is a combination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-perfor.
Manufacture

Cypress

Datasheet
Download CY8C624A Datasheet


Cypress CY8C624A

CY8C624A; mance analog-to-digital conversion and s tandard communication and timing periph erals. Features 32-bit Dual CPU Subsy stem ■ 150-MHz Arm® Cortex®-M4F (CM 4) CPU with single-cycle multiply, floa ting point, and memory protection unit (MPU) ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic operation a t either 1.1 V or 0.9 V ■ .


Cypress CY8C624A

Active CPU current slope with 1.1-V core operation ❐ Cortex-M4: 40 µA/MHz Cortex-M0+: 28 µA/MHz ■ Active CPU current slope with 0.9-V core operatio n ❐ Cortex-M4: 27 µA/MHz ❐ Cortex- M0+: 20 µA/MHz ■ Three DMA controlle rs Memory Subsystem ■ 2048-KB applica tion flash, 32-KB auxiliary flash (AUXf lash), and 32-KB supervisory flash (Sfl ash); read-while-write (RWW) support.


Cypress CY8C624A

. Two 8-KB flash caches, one for each CP U. ■ 1024-KB SRAM with three independ ent blocks for power and data retention control ■ One-time-programmable (OTP ) 1-Kb eFuse array Low-Power 1.7-V to 3 .6-V Operation ■ Six power modes for fine-grained power management ■ Deep Sleep mode current of 7 µA with 64-KB SRAM retention ■ On-chip DC-DC buck c onverter, <1 µA quiescent cur.





Part

CY8C624A

Description

PSoC-62 MCU



Feature


PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet PSoC 62 MCU General Description PSoC ® 6 MCU is a high-performance, ultra-l ow-power and secured MCU platform, purp ose-built for IoT applications. The CY8 C62x8/A product line, based on the PSoC 6 MCU platform, is a combination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-perfor.
Manufacture

Cypress

Datasheet
Download CY8C624A Datasheet




 CY8C624A
PSoC 6 MCU: CY8C62x8,
CY8C62xA Datasheet
PSoC 62 MCU
General Description
PSoC® 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The CY8C62x8/A
product line, based on the PSoC 6 MCU platform, is a combination of a dual CPU microcontroller with low-power flash technology,
digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals.
Features
32-bit Dual CPU Subsystem
150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle
multiply, floating point, and memory protection unit (MPU)
100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply
and MPU
User-selectable core logic operation at either 1.1 V or 0.9 V
Active CPU current slope with 1.1-V core operation
Cortex-M4: 40 µA/MHz
Cortex-M0+: 28 µA/MHz
Active CPU current slope with 0.9-V core operation
Cortex-M4: 27 µA/MHz
Cortex-M0+: 20 µA/MHz
Three DMA controllers
Memory Subsystem
2048-KB application flash, 32-KB auxiliary flash (AUXflash),
and 32-KB supervisory flash (Sflash); read-while-write (RWW)
support. Two 8-KB flash caches, one for each CPU.
1024-KB SRAM with three independent blocks for power and
data retention control
One-time-programmable (OTP) 1-Kb eFuse array
Low-Power 1.7-V to 3.6-V Operation
Six power modes for fine-grained power management
Deep Sleep mode current of 7 µA with 64-KB SRAM retention
On-chip DC-DC buck converter, <1 µA quiescent current
Backup domain with 64 bytes of memory and real-time clock
Flexible Clocking Options
8-MHz internal main oscillator (IMO) with ±2% accuracy
Ultra-low-power 32-kHz internal low-speed oscillator (ILO)
On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)
Two phase-locked loops (PLLs) for multiplying clock
frequencies
Frequency-locked loop (FLL) for multiplying IMO frequency
Integer and fractional peripheral clock dividers
Quad-SPI (QSPI)/Serial Memory Interface (SMIF)
Execute-In-Place (XIP) from external quad SPI flash
On-the-fly encryption and decryption
4-KB cache for greater XIP performance with lower power
Supports single, dual, quad, dual-quad, and octal interfaces
with throughput up to 640 Mbps
Segment LCD Drive
Supports up to 101 segments and up to 8 commons
Serial Communication
13 run-time configurable serial communication blocks (SCBs)
Eight SCBs: configurable as SPI, I2C, or UART
Four SCBs: configurable as I2C or UART
One Deep Sleep SCB: configurable as SPI or I2C
USB Full-Speed device interface
Two independent SD Host Controller/eMMC/SD controllers
Audio Subsystem
Two pulse density modulation (PDM) channels and two I2S
channels with time division multiplexed (TDM) mode
Timing and Pulse-Width Modulation
Thirty-two timer/counter/pulse-width modulators (TCPWMs)
Center-aligned, edge, and pseudo-random modes
Comparator-based triggering of kill signals
Programmable Analog
12-bit 2-Msps SAR ADC with differential and single-ended
modes and 16-channel sequencer with result averaging
Two low-power comparators available in system Deep Sleep
and Hibernate modes
Built-in temperature sensor connected to ADC
Up to 102 Programmable GPIOs
Two Smart I/O™ ports (16 I/Os) enable Boolean operations on
GPIO pins; available during system Deep Sleep
Programmable drive modes, strengths, and slew rates
Six overvoltage-tolerant (OVT) pins
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-23185 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 3, 2021




 CY8C624A
PSoC 6 MCU: CY8C62x8,
CY8C62xA Datasheet
Capacitive Sensing
Cypress CapSense® sigma-delta (CSD) provides best-in-class
signal-to-noise ratio (SNR), liquid tolerance, and proximity
sensing
Enables dynamic usage of both self and mutual sensing
Automatic hardware tuning (SmartSense™)
Security Built into Platform Architecture
ROM-based root of trust via uninterruptible Secured Boot
Authentication during boot using hardware hashing
Step-wise authentication of execution images
Secured execution of code in execute-only mode for protected
routines
All debug and test ingress paths can be disabled
Up to eight protection contexts
Cryptography Accelerator
Hardware acceleration for symmetric and asymmetric
cryptographic methods and hash functions
True random number generator (TRNG) function
Profiler
Eight counters provide event or duration monitoring of on-chip
resources
Packages
128-TQFP, 124-BGA, 100-WLCSP, 68-QFN
Document Number: 002-23185 Rev. *N
Page 2 of 88




 CY8C624A
PSoC 6 MCU: CY8C62x8,
CY8C62xA Datasheet
Contents
Development Ecosystem ................................................. 4
PSoC 6 MCU Resources ............................................. 4
ModusToolbox Software .............................................. 5
Blocks and Functionality ................................................. 6
Functional Description..................................................... 8
CPU and Memory Subsystem ..................................... 8
System Resources .................................................... 12
Programmable Analog Subsystems .......................... 14
Programmable Digital ................................................ 16
Fixed-Function Digital ................................................ 16
GPIO ......................................................................... 18
Special-Function Peripherals .................................... 18
Pinouts ............................................................................ 22
Power Supply Considerations....................................... 38
Electrical Specifications ................................................ 46
Absolute Maximum Ratings ....................................... 46
Device-Level Specifications ...................................... 46
Analog Peripherals .................................................... 55
Digital Peripherals ..................................................... 61
Memory ..................................................................... 64
System Resources .................................................... 65
Ordering Information...................................................... 75
PSoC 6 MPN Decoder .............................................. 76
Packaging........................................................................ 77
Acronyms ........................................................................ 82
Document Conventions ................................................. 84
Units of Measure ....................................................... 84
Revision History ............................................................. 85
Sales, Solutions, and Legal Information ...................... 88
Worldwide Sales and Design Support ....................... 88
Products .................................................................... 88
PSoC® Solutions ...................................................... 88
Cypress Developer Community ................................. 88
Technical Support ..................................................... 88
Document Number: 002-23185 Rev. *N
Page 3 of 88




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