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Microcontrollers. R7FA2L1A92DFM Datasheet

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Part

R7FA2L1A92DFM

Description

Microcontrollers



Feature


Datasheet RA2L1 Group Renesas Microcont rollers R01DS0385EJ0110 Rev.1.10 Feb 2 6, 2021 Ultra low power 48 MHz Arm® C ortex®-M23 core, up to 256-KB code fla sh memory, 32 KB SRAM, Capacitive Sensi ng Unit (CTSU2), 12-bit A/D Converter, 12-bit D/A Converter, Security and Safe ty features. Features ■ Arm Cortex- M23 Core ● Armv8-M architecture ● M aximum operating frequency.
Manufacture

Renesas

Datasheet
Download R7FA2L1A92DFM Datasheet


Renesas R7FA2L1A92DFM

R7FA2L1A92DFM; : 48 MHz ● Arm Memory Protection Unit (Arm MPU) with 8 regions ● Debug and Trace: DWT, FPB, CoreSight™ MTB-M23 CoreSight Debug Port: SW-DP ■ Memo ry ● Up to 256-KB code flash memory 8-KB data flash memory (100,000 prog ram/erase (P/E) cycles) ● 32 KB SRAM ● Memory protection units ● 128-bit unique ID ■ Connectivity ● Serial Communications Interface (SCI) × 5 – Async.


Renesas R7FA2L1A92DFM

hronous interfaces – 8-bit clock synch ronous interface – Simple IIC – Sim ple SPI – Smart card interface ● Se rial Peripheral Interface (SPI) × 2 I2C bus interface (IIC) × 2 ● CAN module (CAN) ■ Analog ● 12-bit A/D Converter (ADC12) ● 12-bit D/A Conver ter (DAC12) ● Low-Power Analog Compar ator (ACMPLP) × 2 ● Temperature Sens or (TSN) ■ Timers ● General PWM Timer 32-bit .


Renesas R7FA2L1A92DFM

(GPT32) × 4 ● General PWM Timer 16-bi t (GPT16) × 6 ● Low Power Asynchrono us General Purpose Timer (AGT) × 2 ● Watchdog Timer (WDT) ● Middle-speed on-chip oscillator (MOCO) (8 MHz) ● Low-speed on-chip oscillator (LOCO) (32 .768 kHz) ● Clock trim function for H OCO/MOCO/LOCO ● IWDT-dedicated on-chi p oscillator (15 kHz) ● Clock out sup port ■ Up to 85 pins for general I/O .





Part

R7FA2L1A92DFM

Description

Microcontrollers



Feature


Datasheet RA2L1 Group Renesas Microcont rollers R01DS0385EJ0110 Rev.1.10 Feb 2 6, 2021 Ultra low power 48 MHz Arm® C ortex®-M23 core, up to 256-KB code fla sh memory, 32 KB SRAM, Capacitive Sensi ng Unit (CTSU2), 12-bit A/D Converter, 12-bit D/A Converter, Security and Safe ty features. Features ■ Arm Cortex- M23 Core ● Armv8-M architecture ● M aximum operating frequency.
Manufacture

Renesas

Datasheet
Download R7FA2L1A92DFM Datasheet




 R7FA2L1A92DFM
Datasheet
RA2L1 Group
Renesas Microcontrollers
R01DS0385EJ0110
Rev.1.10
Feb 26, 2021
Ultra low power 48 MHz Arm® Cortex®-M23 core, up to 256-KB code flash memory, 32 KB SRAM, Capacitive Sensing Unit
(CTSU2), 12-bit A/D Converter, 12-bit D/A Converter, Security and Safety features.
Features
■ Arm Cortex-M23 Core
Armv8-M architecture
Maximum operating frequency: 48 MHz
Arm Memory Protection Unit (Arm MPU) with 8 regions
Debug and Trace: DWT, FPB, CoreSightMTB-M23
CoreSight Debug Port: SW-DP
■ Memory
Up to 256-KB code flash memory
8-KB data flash memory (100,000 program/erase (P/E) cycles)
32 KB SRAM
Memory protection units
128-bit unique ID
■ Connectivity
Serial Communications Interface (SCI) × 5
Asynchronous interfaces
8-bit clock synchronous interface
Simple IIC
Simple SPI
Smart card interface
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 2
CAN module (CAN)
■ Analog
12-bit A/D Converter (ADC12)
12-bit D/A Converter (DAC12)
Low-Power Analog Comparator (ACMPLP) × 2
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-bit (GPT32) × 4
General PWM Timer 16-bit (GPT16) × 6
Low Power Asynchronous General Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
Clock trim function for HOCO/MOCO/LOCO
IWDT-dedicated on-chip oscillator (15 kHz)
Clock out support
■ Up to 85 pins for general I/O ports
5-V tolerance, open drain, input pull-up
■ Operating Voltage
VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
Ta = -40℃ to +85℃
100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
80-pin LQFP (12 mm × 12 mm, 0.5 mm pitch)
64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
48-pin LQFP (7 mm × 7 mm, 0.50 mm pitch)
48-pin HWQFN (7 mm × 7 mm, 0.50 mm pitch)
Ta = -40℃ to +105℃
100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
80-pin LQFP (12 mm × 12 mm, 0.5 mm pitch)
64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
48-pin LQFP (7 mm × 7 mm, 0.50 mm pitch)
48-pin HWQFN (7 mm × 7 mm, 0.50 mm pitch)
■ Safety
ECC in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
■ Security and Encryption
AES128/256
True Random Number Generator (TRNG)
■ System and Power Management
Low power modes
Switching regulator
Realtime Clock (RTC)
Event Link Controller (ELC)
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
■ Human Machine Interface (HMI)
Capacitive Sensing Unit (CTSU2)
■ Multiple Clock Sources
Main clock oscillator (MOSC) 1 to 20 MHz
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO) (24/32/48/64 MHz)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 1 of 111




 R7FA2L1A92DFM
RA2L1 Datasheet
1. Overview
1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability.
The MCU in this series incorporates an energy-efficient Arm Cortex®-M23 32-bit core, that is particularly well suited for
cost-sensitive and low-power applications, with the following features:
Up to 256-KB code flash memory
32-KB SRAM
12-bit A/D Converter (ADC12)
12-bit D/A Converter (DAC12)
Security features
1.1 Function Outline
Table 1.1 Arm core
Feature
Arm Cortex-M23 core
Functional description
● Maximum operating frequency: up to 48 MHz
● Arm Cortex-M23 core:
– Revision: r1p0-00rel0
– Armv8-M architecture profile
– Single-cycle integer multiplier
– 19-cycle integer divider
● Arm Memory Protection Unit (Arm MPU):
– Armv8 Protected Memory System Architecture
– 8 protect regions
● SysTick timer:
– Driven by SYSTICCLK (LOCO) or ICLK
Table 1.2 Memory
Feature
Code flash memory
Data flash memory
Option-setting memory
SRAM
Functional description
Maximum 256 KB of code flash memory.
8 KB of data flash memory.
The option-setting memory determines the state of the MCU after a reset.
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Table 1.3 System (1 of 2)
Feature
Operating modes
Resets
Low Voltage Detection (LVD)
Clocks
Functional description
Two operating modes:
● Single-chip mode
● SCI boot mode
The MCU provides 13 resets. lists the reset names and sources.
The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
See section x, Low Voltage Detection (LVD).
● Main clock oscillator (MOSC)
● Sub-clock oscillator (SOSC)
● High-speed on-chip oscillator (HOCO)
● Middle-speed on-chip oscillator (MOCO)
● Low-speed on-chip oscillator (LOCO)
● IWDT-dedicated on-chip oscillator (IWDTLOCO)
● Clock out support
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 2 of 111




 R7FA2L1A92DFM
RA2L1 Datasheet
1. Overview
Table 1.3 System (2 of 2)
Feature
Clock Frequency Accuracy
Measurement Circuit (CAC)
Interrupt Controller Unit (ICU)
Key Interrupt Function (KINT)
Low power modes
Register write protection
Memory Protection Unit (MPU)
Watchdog Timer (WDT)
Independent Watchdog Timer (IWDT)
Functional description
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock selected as the
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.When measurement is
complete or the number of pulses within the time generated by the measurement reference clock
is not within the allowable range, an interrupt request is generated.
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector
Interrupt Controller (NVIC), and the Data Transfer Controller (DTC) modules. The ICU also
controls non-maskable interrupts.
The key interrupt function (KINT) generates the key interrupt by detecting rising or falling edge
on the key interrupt input pins.
Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
The MCU has four Memory Protection Units (MPUs) and a CPU stack pointer monitor function
are provided.
The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow
interrupt or watchdog timer reset.
The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the
MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer
operates with an independent, dedicated clock source, it is particularly useful in returning the
MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT
can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value
in the registers.
Table 1.4 Event link
Feature
Event Link Controller (ELC)
Functional description
The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between the
modules without CPU intervention.
Table 1.5 Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.
Table 1.6 Timers (1 of 2)
Feature
General PWM Timer (GPT)
Port Output Enable for GPT (POEG)
Low power Asynchronous General
Purpose Timer (AGT)
Functional description
The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with
GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, down-
counter, or the up- and down-counter. In addition, PWM waveforms can be generated for
controlling brushless DC motors. The GPT can also be used as a general-purpose timer.
The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins
in the output disable state
The low power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used
for pulse output, external pulse width or period measurement, and counting external events. This
timer consists of a reload register and a down counter. The reload register and the down counter
are allocated to the same address, and can be accessed with the AGT register.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 3 of 111




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