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Microcontrollers. R7FA6M5AH3CFB Datasheet

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Part

R7FA6M5AH3CFB

Description

Microcontrollers



Feature


Datasheet RA6M5 Group Renesas Microcont rollers R01DS0366EJ0110 Rev.1.10 Mar 3 1, 2021 High-performance 200 MHz Arm C ortex-M33 core, up to 2 MB code flash m emory with Dual-bank, background and SW AP operation, 8 KB Data flash memory, a nd 512 KB SRAM with Parity/ECC. High-in tegration with Ethernet MAC controller, USB 2.0 High-Speed, CAN FD, SDHI, Quad and Octa SPI, and.
Manufacture

Renesas

Datasheet
Download R7FA6M5AH3CFB Datasheet


Renesas R7FA6M5AH3CFB

R7FA6M5AH3CFB; advanced analog. Integrated Secure Cryp to Engine with cryptography accelerator s, key management support, tamper detec tion and power analysis resistance in c oncert with Arm TrustZone for integrate d secure element functionality. Featur es ■ Arm® Cortex®-M33 Core ● Armv 8-M architecture with the main extensio n ● Maximum operating frequency: 200 MHz ● Arm Memory Protectio.


Renesas R7FA6M5AH3CFB

n Unit (Arm MPU) – Protected Memory Sy stem Architecture (PMSAv8) – Secure M PU (MPU_S): 8 regions – Non-secure MP U (MPU_NS): 8 regions ● SysTick timer – Embeds two Systick timers: Secure and Non-secure instance – Driven by L OCO or system clock ● CoreSight™ ET M-M33 ■ Memory ● Up to 2-MB code fl ash memory ● 8-KB data flash memory ( 100,000 program/erase (P/E) cycles) ● 51.


Renesas R7FA6M5AH3CFB

2-KB SRAM ■ Connectivity ● Serial Co mmunications Interface (SCI) × 10 – Asynchronous interfaces – 8-bit clock synchronous interface – Smart card i nterface – Simple IIC – Simple SPI – Manchester coding (SCI3, SCI4) ● I2C bus interface (IIC) × 3 ● Serial Peripheral Interface (SPI) × 2 ● Qu ad Serial Peripheral Interface (QSPI) Octa Serial Peripheral Interface (OSPI) ● .





Part

R7FA6M5AH3CFB

Description

Microcontrollers



Feature


Datasheet RA6M5 Group Renesas Microcont rollers R01DS0366EJ0110 Rev.1.10 Mar 3 1, 2021 High-performance 200 MHz Arm C ortex-M33 core, up to 2 MB code flash m emory with Dual-bank, background and SW AP operation, 8 KB Data flash memory, a nd 512 KB SRAM with Parity/ECC. High-in tegration with Ethernet MAC controller, USB 2.0 High-Speed, CAN FD, SDHI, Quad and Octa SPI, and.
Manufacture

Renesas

Datasheet
Download R7FA6M5AH3CFB Datasheet




 R7FA6M5AH3CFB
Datasheet
RA6M5 Group
Renesas Microcontrollers
R01DS0366EJ0110
Rev.1.10
Mar 31, 2021
High-performance 200 MHz Arm Cortex-M33 core, up to 2 MB code flash memory with Dual-bank, background and SWAP
operation, 8 KB Data flash memory, and 512 KB SRAM with Parity/ECC. High-integration with Ethernet MAC controller, USB
2.0 High-Speed, CAN FD, SDHI, Quad and Octa SPI, and advanced analog. Integrated Secure Crypto Engine with
cryptography accelerators, key management support, tamper detection and power analysis resistance in concert with Arm
TrustZone for integrated secure element functionality.
Features
Arm® Cortex®-M33 Core
Armv8-M architecture with the main extension
Maximum operating frequency: 200 MHz
Arm Memory Protection Unit (Arm MPU)
Protected Memory System Architecture (PMSAv8)
Secure MPU (MPU_S): 8 regions
Non-secure MPU (MPU_NS): 8 regions
SysTick timer
Embeds two Systick timers: Secure and Non-secure instance
Driven by LOCO or system clock
CoreSightETM-M33
■ Memory
Up to 2-MB code flash memory
8-KB data flash memory (100,000 program/erase (P/E) cycles)
512-KB SRAM
■ Connectivity
Serial Communications Interface (SCI) × 10
Asynchronous interfaces
8-bit clock synchronous interface
Smart card interface
Simple IIC
Simple SPI
Manchester coding (SCI3, SCI4)
I2C bus interface (IIC) × 3
Serial Peripheral Interface (SPI) × 2
Quad Serial Peripheral Interface (QSPI)
Octa Serial Peripheral Interface (OSPI)
USB 2.0 Full-Speed Module (USBFS)
USB 2.0 High-Speed Module (USBHS)
CAN with Flexible Data-rate (CANFD) × 2
Ethernet MAC/DMA Controller (ETHERC/EDMAC)
SD/MMC Host Interface (SDHI)
Serial Sound Interface Enhanced (SSIE)
Consumer Electronics Control (CEC)
Realtime Clock (RTC) with calendar and VBATT support
Event Link Controller (ELC)
Data Transfer Controller (DTC)
DMA Controller (DMAC) × 8
Power-on reset
Low Voltage Detection (LVD) with voltage settings
Watchdog Timer (WDT)
Independent Watchdog Timer (IWDT)
■ Human Machine Interface (HMI)
Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
Main clock oscillator (MOSC) (8 to 24 MHz)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
PLL/PLL2
Clock out support
■ General-Purpose I/O Ports
5-V tolerance, open drain, input pull-up, switchable driving ability
■ Operating Voltage
VCC: 2.7 to 3.6 V
■ Operating Temperature and Packages
Ta = -40℃ to +105℃
176-pin LQFP (24 mm × 24 mm, 0.5 mm pitch)
144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
Ta = -40℃ to +85℃
176-pin BGA (13 mm × 13 mm, 0.8 mm pitch)
■ Analog
12-bit A/D Converter (ADC12) × 2
- 5 Msps at interleaving
12-bit D/A Converter (DAC12) × 2
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-bit (GPT32) × 4
General PWM Timer 16-bit (GPT16) × 6
Low Power Asynchronous General Purpose Timer (AGT) × 6
■ Security and Encryption
Secure Crypto Engine 9
Symmetric algorithms: AES
Asymmetric algorithms: RSA, ECC, and DSA
Hash-value generation: SHA224, SHA256, GHASH
128-bit unique ID
Arm® TrustZone®
Up to three or six regions for the code flash, depending on the
bank mode
Up to two regions for the data flash
Up to three regions for the SRAM
Individual secure or non-secure security attribution for each
peripheral
Device lifecyle management
Pin function
Up to three tamper pins
Secure pin multiplexing
■ System and Power Management
Low power modes
Battery backup function (VBATT)
R01DS0366EJ0110 Rev.1.10
Mar 31, 2021
Page 1 of 118




 R7FA6M5AH3CFB
RA6M5 Datasheet
1. Overview
1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to 200 MHz with the following
features:
Up to 2 MB code flash memory
512 KB SRAM
Quad Serial Peripheral Interface (QSPI), Octa Serial Peripheral Interface (OSPI)
Ethernet MAC Controller (ETHERC), USBFS, USBHS, SD/MMC Host Interface
Capacitive Touch Sensing Unit (CTSU)
Analog peripherals
Security and safety features
1.1 Function Outline
Table 1.1 Arm core
Feature
Arm Cortex-M33 core
Table 1.2 Memory
Feature
Code flash memory
Data flash memory
Option-setting memory
SRAM
Table 1.3 System (1 of 2)
Feature
Operating modes
Resets
Low Voltage Detection (LVD)
Functional description
● Maximum operating frequency: up to 200 MHz
● Arm Cortex-M33 core:
– Armv8-M architecture with security extension
– Revision: r0p4-00rel0
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)
● CoreSightETM-M33
Functional description
Maximum 2 MB of code flash memory.
8 KB of data flash memory.
The option-setting memory determines the state of the MCU after a reset.
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Functional description
Two operating modes:
● Single-chip mode
● SCI/USB boot mode
The MCU provides 14 resets.
The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
R01DS0366EJ0110 Rev.1.10
Mar 31, 2021
Page 2 of 118




 R7FA6M5AH3CFB
RA6M5 Datasheet
1. Overview
Table 1.3
Feature
Clocks
System (2 of 2)
Clock Frequency Accuracy
Measurement Circuit (CAC)
Interrupt Controller Unit (ICU)
Low power modes
Battery backup function
Register write protection
Memory Protection Unit (MPU)
Functional description
● Main clock oscillator (MOSC)
● Sub-clock oscillator (SOSC)
● High-speed on-chip oscillator (HOCO)
● Middle-speed on-chip oscillator (MOCO)
● Low-speed on-chip oscillator (LOCO)
● IWDT-dedicated on-chip oscillator
● PLL/PLL2
● Clock out support
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock selected as the
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.When measurement is
complete or the number of pulses within the time generated by the measurement reference clock
is not within the allowable range, an interrupt request is generated.
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector
Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC)
modules. The ICU also controls non-maskable interrupts.
Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
A battery backup function is provided for partial powering by a battery. The battery-powered area
includes the RTC, SOSC, backup memory, and switch between VCC and VBATT.
The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
The MCU has one Memory Protection Unit (MPU).
Table 1.4 Event link
Feature
Event Link Controller (ELC)
Functional description
The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between the
modules without CPU intervention.
Table 1.5 Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.
DMA Controller (DMAC)
The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer data
without intervention from the CPU. When a DMA transfer request is generated, the DMAC
transfers data stored at the transfer source address to the transfer destination address.
Table 1.6 External bus interface
Feature
Functional description
External buses
● CS area (ECBIU): Connected to the external devices (external memory interface)
● QSPI area (EQBIU): Connected to the QSPI (external device interface)
● OSPI area (EOBIU): Connected to the OSPI (external device interface)
Table 1.7 Timers (1 of 2)
Feature
General PWM Timer (GPT)
Port Output Enable for GPT (POEG)
Functional description
The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with
GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, down-
counter, or the up- and down-counter. In addition, PWM waveforms can be generated for
controlling brushless DC motors. The GPT can also be used as a general-purpose timer.
The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins
in the output disable state
R01DS0366EJ0110 Rev.1.10
Mar 31, 2021
Page 3 of 118




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