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Fanout Buffer. 83210 Datasheet

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Fanout Buffer. 83210 Datasheet
















83210 Buffer. Datasheet pdf. Equivalent













Part

83210

Description

HSTL Fanout Buffer



Feature


Low Skew, 1-to-10, HSTL Fanout Buffer 8 3210 Data Sheet GENERAL DESCRIPTION Th e 83210 is a low skew, 1-to-10 HSTL Fan out Buffer. The class II HSTL outputs a re balanced push-pull in design, capabl e of delivering 16mA into a 10pF load. This class allows both source series te rmination and symmetrically double para llel termination. FEATURES • Ten sin gle-ended HSTL outpu.
Manufacture

Renesas

Datasheet
Download 83210 Datasheet


Renesas 83210

83210; ts • One single-ended HSTL clock input • Maximum input frequency: 150MHz Output skew: 110ps (maximum) • Part -to-part skew: 2ns (maximum) • 1.5V p ower supply • 0°C to 85°C ambient o perating temperature • Available in l ead-free (RoHS 6) package BLOCK DIAGRA M IN nOE Pulldown PIN ASSIGNMENT GND Q2 Q1 VDD VDD Q0 GND GND Q0 32 31 30 29 28 27 26 25 Q1 VDD 1 24 GND .


Renesas 83210

GND 2 23 Q3 VDD 3 22 Q4 nOE 4 21 V DD Q8 GND 5 ICS83210 20 VDD Q9 IN 6 19 Q5 VDD 7 18 Q6 GND 8 17 GND 9 10 11 12 13 14 15 16 GND Q7 Q8 VDD VDD Q9 GND GND 32-Lead TQFP 7mm x 7mm x 1.0mm package body Y package Top View ©2016 Integrated Device Technology, Inc 1 Revision A March 10, 2016 8321 0 Data Sheet TABLE 1. PIN DESCRIPTIONS Number 1, 3, 7, 1.


Renesas 83210

2, 13, 20, 21, 28, 29 2, 5, 8, 9, 10, 16 , 17, 24, 25, 31, 32 4 Name V DD GND n OE Type Power Description Power suppl y pins. Power Power supply ground. I nput Output enable/disable input pin. When LOW, outputs Qx outputs are Pulldo wn enabled. When HIGH, Qx outputs are d isabled low. LVCMOS/LVTTL interface lev els. 5 IN Input Single-ended refere nce clock input. H.





Part

83210

Description

HSTL Fanout Buffer



Feature


Low Skew, 1-to-10, HSTL Fanout Buffer 8 3210 Data Sheet GENERAL DESCRIPTION Th e 83210 is a low skew, 1-to-10 HSTL Fan out Buffer. The class II HSTL outputs a re balanced push-pull in design, capabl e of delivering 16mA into a 10pF load. This class allows both source series te rmination and symmetrically double para llel termination. FEATURES • Ten sin gle-ended HSTL outpu.
Manufacture

Renesas

Datasheet
Download 83210 Datasheet




 83210
Low Skew, 1-to-10, HSTL Fanout Buffer
83210
Data Sheet
GENERAL DESCRIPTION
The 83210 is a low skew, 1-to-10 HSTL Fanout Buffer.
The class II HSTL outputs are balanced push-pull in design, capable
of delivering 16mA into a 10pF load. This class allows both source
series termination and symmetrically double parallel termination.
FEATURES
Ten single-ended HSTL outputs
One single-ended HSTL clock input
Maximum input frequency: 150MHz
Output skew: 110ps (maximum)
Part-to-part skew: 2ns (maximum)
1.5V power supply
0°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
IN
nOE Pulldown
PIN ASSIGNMENT
Q0
32 31 30 29 28 27 26 25
Q1
VDD 1
24 GND
GND 2
23 Q3
VDD 3
22 Q4
nOE 4
21 VDD
Q8
GND 5
ICS83210
20 VDD
Q9
IN 6
19 Q5
VDD 7
18 Q6
GND 8
17 GND
9 10 11 12 13 14 15 16
32-Lead TQFP
7mm x 7mm x 1.0mm package body
Y package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 10, 2016




 83210
83210 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
1, 3, 7, 12, 13,
20, 21, 28, 29
2, 5, 8, 9, 10,
16, 17, 24, 25, 31, 32
4
Name
V
DD
GND
nOE
Type
Power
Description
Power supply pins.
Power
Power supply ground.
Input
Output enable/disable input pin. When LOW, outputs Qx outputs are
Pulldown enabled. When HIGH, Qx outputs are disabled low.
LVCMOS/LVTTL interface levels.
5
IN
Input
Single-ended reference clock input. HSTL interface levels.
11, 14, 15,
18, 19, 22,
23, 26, 27, 30
Q9, Q8, Q7, Q6,
Q5, Q4, Q3, Q2, Output
Q1, Q0
Single-ended HSTL clock outputs.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C
IN
R
PULLDOWN
C
OUT
R
OUT
Input Capacitance
Input Pulldown Resistor
Output Pin Capacitance
Output Impedance
Test Conditions
Minimum
Typical
4
51
4.5
20
Maximum
6
Units
pF
kΩ
pF
Ω
©2016 Integrated Device Technology, Inc
2
Revision A March 10, 2016




 83210
83210 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance, θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V + 0.5 V
DD
-0.5V to V + 0.5V
DD
75.5°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V = 1.5V ± 8%, TA = 0°C TO 85°C
DD
Symbol Parameter
Test Conditions
V
Power Supply Voltage
DD
I
Power Supply Current
DD
I
Quiescent Supply Current
DDQ
Outputs Loaded @ 62.5MHz
V = 0V, outputs disabled
IN
Minimum
1.38
Typical
1.5
215
Maximum
1.62
250
1
Units
V
mA
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V = 1.5V ± 8%, TA = 0°C TO 85°C
DD
Symbol Parameter
Test Conditions
Minimum
V
Input High Voltage nOE
IH
V
Input Low Voltage nOE
IL
I
Input High Current nOE
IH
I
Input Low Current nOE
IL
0.7*V
DD
-0.3
-5
Typical
Maximum
V + 0.3
DD
0.3*V
DD
150
Units
V
V
µA
µA
TABLE 3C. HSTL DC CHARACTERISTICS, V = 1.5V ± 8%, TA = 0°C TO 85°C
DD
Symbol Parameter
Test Conditions
V
Input High Voltage IN
IH
V
Input Low Voltage IN
IL
V
Output High Voltage
OH
V
Output Low Voltage
OL
V = 0.75V
REF
I = -16mA
OH
I = 16mA
OL
Minimum
0.85
-0.3
1.0
-0.3
Typical
Maximum
1.8
0.65
V + 0.3
DD
0.4
Units
V
V
V
V
©2016 Integrated Device Technology, Inc
3
Revision A March 10, 2016




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