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Applications Processor. MIMX8MM4CVTKZAA Datasheet
















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Part

MIMX8MM4CVTKZAA

Description

i.MX 8M Mini Applications Processor



Feature


NXP Semiconductors Data Sheet: Technical Data Document Number: IMX8MMIEC Rev. 1, 07/2020 i.MX 8M Mini Applications P rocessor Datasheet for Industrial Produ cts MIMX8MM6CVTKZAA MIMX8MM4CVTKZAA MI MX8MM2CVTKZAA MIMX8MM5CVTKZAA MIMX8MM3 CVTKZAA MIMX8MM1CVTKZAA Package Inform ation Plastic Package FCBGA 14 x 14 mm, 0.5 mm pitch Ordering Information See Table 2 on page 6.
Manufacture

NXP

Datasheet
Download MIMX8MM4CVTKZAA Datasheet


NXP MIMX8MM4CVTKZAA

MIMX8MM4CVTKZAA; 1 i.MX 8M Mini introduction The i.MX 8M Mini applications processor represen ts 1. i.MX 8M Mini introduction . . . . . . . . . . . . . . . . . . . . . . . . 1 NXP’s latest video and audio exp erience combining 1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 state-of-the-art med ia-specific features with 2. 1.2. O rdering information .


NXP MIMX8MM4CVTKZAA

. . . . . . . . . . . . . . . . . . . . . . . 6 Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 high-performance proces sing while optimized for lowest 2.1. Re commended connections for unused input/ output 12 power consumption. 3. Elect rical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1. Chip-level conditi.


NXP MIMX8MM4CVTKZAA

ons . . . . . . . . . . . . . . . . . . . . . . 14 The i.MX 8M Mini family of processors features advanced implementa tion of a quad Arm® Cor- 3.2. Power s upplies requirements and restrictions . . . 22 3.3. PLL electrical characteris tics . . . . . . . . . . . . . . . . 26 3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 27 tex®-A53 core, whic.





Part

MIMX8MM4CVTKZAA

Description

i.MX 8M Mini Applications Processor



Feature


NXP Semiconductors Data Sheet: Technical Data Document Number: IMX8MMIEC Rev. 1, 07/2020 i.MX 8M Mini Applications P rocessor Datasheet for Industrial Produ cts MIMX8MM6CVTKZAA MIMX8MM4CVTKZAA MI MX8MM2CVTKZAA MIMX8MM5CVTKZAA MIMX8MM3 CVTKZAA MIMX8MM1CVTKZAA Package Inform ation Plastic Package FCBGA 14 x 14 mm, 0.5 mm pitch Ordering Information See Table 2 on page 6.
Manufacture

NXP

Datasheet
Download MIMX8MM4CVTKZAA Datasheet




 MIMX8MM4CVTKZAA
NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX8MMIEC
Rev. 1, 07/2020
i.MX 8M Mini Applications
Processor Datasheet for
Industrial Products
MIMX8MM6CVTKZAA
MIMX8MM4CVTKZAA
MIMX8MM2CVTKZAA
MIMX8MM5CVTKZAA
MIMX8MM3CVTKZAA
MIMX8MM1CVTKZAA
Package Information
Plastic Package
FCBGA 14 x 14 mm, 0.5 mm pitch
Ordering Information
See Table 2 on page 6
1 i.MX 8M Mini introduction
The i.MX 8M Mini applications processor represents 1. i.MX 8M Mini introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
NXP’s latest video and audio experience combining 1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
state-of-the-art
media-specific
features
with
2.
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
high-performance processing while optimized for lowest 2.1. Recommended connections for unused input/output 12
power consumption.
3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 14
The i.MX 8M Mini family of processors features
advanced implementation of a quad Arm® Cor-
3.2. Power supplies requirements and restrictions . . . 22
3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 26
3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 27
tex®-A53 core, which operates at speeds of up to
1.6 GHz. A general purpose Cortex®-M4 400 MHz
3.5. General purpose I/O (GPIO) DC parameters . . . 28
3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 29
3.7. Output buffer impedance parameters . . . . . . . . . 30
core processor is for low-power processing. The DRAM
3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 32
controller supports 32-bit/16-bit LPDDR4, DDR4, and
DDR3L memory. A wide range of audio interfaces are
3.9. External peripheral interface parameters . . . . . . 33
4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 68
available, including I2S, AC97, TDM, and S/PDIF.
There are a number of other interfaces for connecting
peripherals, such as USB, PCIe, and Ethernet.
4.2. Boot device interface allocation . . . . . . . . . . . . . . 69
5. Package information and contact assignments . . . . . . . 70
5.1. 14 x 14 mm package information . . . . . . . . . . . . 70
5.2. DDR pin function list . . . . . . . . . . . . . . . . . . . . . . 87
6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.




 MIMX8MM4CVTKZAA
i.MX 8M Mini introduction
Subsystem
Arm Cortex-A53 MPCore platform
Arm Cortex-M4 core platform
Connectivity
On-chip memory
GPIO and pin multiplexing
Power management
Table 1. Features
Features
Quad symmetric Cortex-A53 processors
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Media Processing Engine (MPE) with NEON technology supporting the Advanced
Single Instruction Multiple Data architecture:
• Floating Point Unit (FPU) with support of the VFPv4-D16 architecture
Support of 64-bit Armv8-A architecture
512 KB unified L2 cache
Low power microcontroller available for customer application:
• low power standby mode
• IoT features including Weave
• Manage IR or Wireless Remote
Cortex M4 CPU:
• 16 KB L1 Instruction Cache
• 16 KB L1 Data Cache
• 256 KB tightly coupled memory (TCM)
One PCI Express (PCIe)
• Single lane supporting PCIe Gen2
• Dual mode operation to function as root complex or endpoint
• Integrated PHY interface
• Support L1 low power sub-state
Two USB 2.0 OTG controllers with integrated PHY interfaces:
• Spread spectrum clock support
Three Ultra Secure Digital Host Controller (uSDHC) interfaces:
• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec
• SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100
MB/sec
• Support for SDXC (extended capacity)
One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),
Ethernet AVB, and IEEE 1588
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Four I2C modules
Three ECSPI modules
Boot ROM (256 KB)
On-chip RAM (256 KB + 32 KB)
General-purpose input/output (GPIO) modules with interrupt capability
Input/output multiplexing controller (IOMUXC) to provide centralized pad control
Temperature sensor with programmable trip points
Flexible power domain partitioning with internal power switches to support efficient
power management
i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 1, 07/2020
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NXP Semiconductors




 MIMX8MM4CVTKZAA
Subsystem
External memory interface
Multimedia
System debug
i.MX 8M Mini introduction
Table 1. Features (continued)
Features
32/16-bit DRAM interfaces:
• LPDDR4 (up to 1.5 GHz)
• DDR4-2400
• DDR3L-1600
8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
eMMC 5.1 Flash (2 interfaces, uSDHC1 and uSDHC3)
SPI NOR Flash (3 interfaces)
FlexSPI with support for XIP (for ME in low-power mode) and parallel read mode of
two identical FLASH devices
Video Processing Unit:
• 1080p60 VP9 Profile 0, 2 (10-bit)
• 1080p60 HEVC/H.265 Decoder
• 1080p60 AVC/H.264 Baseline, Main, High decoder
• 1080p60 VP8
• 1080p60 AVC/H.264 Encoder
• 1080p60 VP8
• TrustZone support
Graphic Processing Unit:
• GCNanoUltra for 3D acceleration
• GC320 for 2D acceleration
LCDIF Display Controller:
• Support up to 2 layers of overlay
• Support up to 1080p60 display through MIPI DSI
MIPI Interface:
• 4-lane MIPI CSI interface
• 4-lane MIPI DSI interface
Audio:
• S/PDIF input and output, including a new Raw Capture input mode
• Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM,
codec/DSP, and DSD interfaces, including one SAI with 8 Tx and 8 Rx lanes, one
SAI with 4 Tx and 4 Rx lanes, two SAI with 2 Tx and 2 Rx lanes, and one SAI with
1 Tx and 1Rx lane. Support over 20 channels of audio subject to I/O limitations.
• 8-Channel Pulse Density Modulation (PDM) input
Arm CoreSight debug and trace architecture
Trace Port Interface Unit (TPIU) to support off-chip real-time trace
Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering
Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs
Cross Triggering Interface (CTI)
Support for 5-pin (JTAG) debug interface
i.MX 8M Mini Applications Processor Datasheet for Industrial Products, Rev. 1, 07/2020
NXP Semiconductors
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