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Part

MIMX8QP6AVUFFAB

Description

i.MX 8QuadPlus Automotive and Infotainment Applications Processors



Feature


NXP Semiconductors Data Sheet: Technical Data IMX8QPAEC Rev. 2, 05/2021 MIMX8Q PnAVUxxAx i.MX 8QuadPlus Automotive an d Infotainment Applications Processors Package Information 29 x 29 mm package case outline Ordering Information See Table 2 on page 5 1 Introduction The i.MX 8 Family consists of two processor s: i.MX 8QuadMax and 8QuadPlus. This da ta sheet covers th.
Manufacture

NXP

Datasheet
Download MIMX8QP6AVUFFAB Datasheet


NXP MIMX8QP6AVUFFAB

MIMX8QP6AVUFFAB; e i.MX 8QuadPlus processor, which is com posed of seven cores (one Arm® Cortex -A72, four Arm Cortex®-A53, and two A rm Cortex®-M4F), dual 32-bit GPU subsy stems, 4K H.265 capable VPU, and dual f ailover-ready display controllers. This processor supports a single 4K display (with multiple display output options, including MIPI-DSI, HDMI, eDP/DP, and LVDS), or multiple sma.


NXP MIMX8QP6AVUFFAB

ller displays. Memory interfaces support ing LPDDR4, Quad SPI/Octal SPI (FlexSPI ), eMMC 5.1, RAW NAND, SD 3.0, and a wi de range of peripheral I/Os such as PCI e 3.0, provide wide flexibility. Advanc ed multicore audio processing is suppor ted by the Arm cores and a high perform ance Tensilica® HiFi 4 DSP for pre- an d post-audio processing as well as voic e recognition. 1 I.


NXP MIMX8QP6AVUFFAB

ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 System Controller Firmware (SCF W) Requirements5 1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 .





Part

MIMX8QP6AVUFFAB

Description

i.MX 8QuadPlus Automotive and Infotainment Applications Processors



Feature


NXP Semiconductors Data Sheet: Technical Data IMX8QPAEC Rev. 2, 05/2021 MIMX8Q PnAVUxxAx i.MX 8QuadPlus Automotive an d Infotainment Applications Processors Package Information 29 x 29 mm package case outline Ordering Information See Table 2 on page 5 1 Introduction The i.MX 8 Family consists of two processor s: i.MX 8QuadMax and 8QuadPlus. This da ta sheet covers th.
Manufacture

NXP

Datasheet
Download MIMX8QP6AVUFFAB Datasheet




 MIMX8QP6AVUFFAB
NXP Semiconductors
Data Sheet: Technical Data
IMX8QPAEC
Rev. 2, 05/2021
MIMX8QPnAVUxxAx
i.MX 8QuadPlus
Automotive and
Infotainment
Applications Processors
Package Information
29 x 29 mm package case outline
Ordering Information
See Table 2 on page 5
1 Introduction
The i.MX 8 Family consists of two processors:
i.MX 8QuadMax and 8QuadPlus. This data sheet covers
the i.MX 8QuadPlus processor, which is composed of
seven cores (one Arm® Cortex®-A72, four Arm
Cortex®-A53, and two Arm Cortex®-M4F), dual 32-bit
GPU subsystems, 4K H.265 capable VPU, and dual
failover-ready display controllers. This processor
supports a single 4K display (with multiple display
output options, including MIPI-DSI, HDMI, eDP/DP,
and LVDS), or multiple smaller displays. Memory
interfaces supporting LPDDR4, Quad SPI/Octal SPI
(FlexSPI), eMMC 5.1, RAW NAND, SD 3.0, and a wide
range of peripheral I/Os such as PCIe 3.0, provide wide
flexibility. Advanced multicore audio processing is
supported by the Arm cores and a high performance
Tensilica® HiFi 4 DSP for pre- and post-audio
processing as well as voice recognition.
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 System Controller Firmware (SCFW) Requirements5
1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 13
3.2 Recommended Connections for Unused Interfaces13
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Power supplies requirements and restrictions. . . . 26
4.3 PLL electrical characteristics . . . . . . . . . . . . . . . . . 29
4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36
4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7 Output Buffer Impedance Parameters. . . . . . . . . . 45
4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 49
4.9 General-Purpose Media Interface (GPMI) Timing . 53
4.10 External Peripheral Interface Parameters . . . . . . . 62
4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 111
5 Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1 Boot mode configuration inputs. . . . . . . . . . . . . . 115
5.2 Boot devices interfaces allocation . . . . . . . . . . . . 115
6 Package information and contact assignments . . . . . . 117
6.1 FCPBGA, 29 x 29 mm, 0.75 mm pitch . . . . . . . . 117
7 Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.
© 2018-2021 NXP B.V.




 MIMX8QP6AVUFFAB
Introduction
The i.MX 8QuadPlus processor offers numerous advanced features as shown in this table.
Table 1. i.MX 8QuadPlus advanced features
Function
Feature
Multicore architecture provides
4× Cortex-A53, Cortex-A72 cores,
and 2× Cortex-M4F cores
Graphics Processing Unit (GPU)
Video Processing Unit (VPU)
Tensilica HiFi 4 DSP for pre- and
post-processing
Memory
AArch64 for 64-bit support and new architectural features
AArch32 for full backward compatibility with ARMv7
Cortex-A72 and Cortex-A53 cores support ARM virtualization extensions. sMMU
provides address virtualization to all subsystems.
Cortex-M4F cores for real-time applications
16× Vec4 shaders with 64 execution units. Split GPU architecture allows for dual
independent 8-Vec4 shader GPUs or a combined 16-Vec4 shader GPU.
Supports OpenGL 3.0, 2.1,; OpenGL ES 3.2, 3.1 (with AEP), 3.0, 2.0, and 1.1;
OpenCL 1.2 Full Profile and 1.1; OpenVG 1.1; and Vulkan
High-performance 2D Blit Engine
H.265 decode (4Kp60)
H.264 decode (4Kp30)
WMV9/VC-1 imple decode
MPEG 1 and 2 decode
AVS decode
MPEG4.2 ASP, H.263, Sorenson Spark decode
Divx 3.11 including GMC decode
ON2/Google VP6/VP8 decode
RealVideo 8/9/10 decode
JPEG and MJPEG decode
H.264 encode (1080p30)
666 MHz
Fixed-point and vector-floating-point support
32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and
64 KB of TCM)
64-bit LPDDR4 @1600 MHz
1× Quad SPI which can be used to connect to an FPGA
2× Quad SPI or 1× Octal SPI (FlexSPI) for fast boot from SPI NOR flash
2× SD 3.0 card interfaces
1× eMMC5.1/SD3.0
RAW NAND (62-bit ECC support via BCH-62 module)
i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021
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NXP Semiconductors




 MIMX8QP6AVUFFAB
Function
Display Controller
Display I/O
Camera I/O and video
Security
System Control
Introduction
Table 1. i.MX 8QuadPlus advanced features (continued)
Feature
Supports single UltraHD 4Kp60 display or up to 4 independent FullHD 1080p60
displays
Up to 18-layer composition
Complementary 2D blitting engines and online warping functionality
Integrated Failover Path (SafeAssure) to ensure display content stays valid even in
event of a software failure
2× MIPI-DSI with 4 lanes each
1× HDMI-TX/DisplayPort compliant with:
• HDMI
• eDP 1.4
• DP 1.3
This high performance serializer supports a pair of LVDS displays with 8 lanes each.
Each port can be configured for 2x Tx with 4 lanes each.
2× MIPI-CSI with 4-lanes each
Advanced High Assurance Boot (AHAB) secure & encrypted boot
Random Number Generator with a high-quality entropy source generator and
Hash_DRBG (based on hash functions)
RSA up to 4096, Elliptic Curve up to 1023
AES-128/192/256, DES, 3DES, MD5, SHA-1, SHA-224/256/384/512
Dedicated Security Controller for Flashless SHE and HSM support, Trustzone
Built-in ECDSA/DSA protocol support
See the security reference manual for this chip for a full list of security features.
• 2× I2C tightly coupled with Cortex-M4 cores (1× per Cortex M4F core)
• The tightly coupled M4 I2C ports cannot be used for general-purpose use
• System Control Unit (SCU):
• Power control, clocks, reset
• Boot ROMs
• PMIC interface
• Resource Domain Controller
i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021
NXP Semiconductors
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