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secure microcontroller. P60D145_SDS Datasheet

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secure microcontroller. P60D145_SDS Datasheet
















P60D145_SDS microcontroller. Datasheet pdf. Equivalent













Part

P60D145_SDS

Description

dual interface secure microcontroller



Feature


P60D145_SDS SmartMX2 Family P60D145y Rev . 3.0 — 27 September 2016 Public pro duct data sheet COMPANY PUBLIC 1 Gener al description The P60D145 dual interfa ce secure microcontroller is part of th e most recent P60Step-Up! family genera tion and builds on the IntegralSecurity architecture. It delivers unprecedente d security, extended memory footprint, and highest performa.
Manufacture

NXP

Datasheet
Download P60D145_SDS Datasheet


NXP P60D145_SDS

P60D145_SDS; nce across all typical up-to-date reques ted fast transaction cases in Payment a nd eGov. Furthermore, it comes with com prehensive options of ready-to-use MIFA RE™ functionality and certified crypt o library modules and can be ordered in various advanced package options for c ontact, dual interface, and contactless operation. 2 Features and benefits 2. 1 Key features • Use.


NXP P60D145_SDS

r EEPROM: up to 142,5 KB • User ROM: 512 KB, y = P or M or D or J – 586 KB, y = X • User RAM: up to 10176 By tes • Dual Interface Type according t o ISO/IEC 14443/7816 • Rich option ch oice of certified convergence implement ations: – y = P (Plain, no convergenc e implementations) – y = X (Plain, no convergence implementations, extended User ROM) – y = M (MIFARE Plus/Cla.


NXP P60D145_SDS

ssic implementation) – y = D (MIFARE D ESFire EV1 implementation) – y = J (J oint, common MIFARE Plus/Classic/DESFir e EV1 implementation) • Contactless V HBR data rate up to 1.7 Mbit/s (card to reader) • Hardware-based Physically Unclonable Function (PUF) implemented: provides strong protection for secret k eys and data • SmartICE Development t ool chain with true bond-out.





Part

P60D145_SDS

Description

dual interface secure microcontroller



Feature


P60D145_SDS SmartMX2 Family P60D145y Rev . 3.0 — 27 September 2016 Public pro duct data sheet COMPANY PUBLIC 1 Gener al description The P60D145 dual interfa ce secure microcontroller is part of th e most recent P60Step-Up! family genera tion and builds on the IntegralSecurity architecture. It delivers unprecedente d security, extended memory footprint, and highest performa.
Manufacture

NXP

Datasheet
Download P60D145_SDS Datasheet




 P60D145_SDS
P60D145_SDS
SmartMX2 Family P60D145y
Rev. 3.0 — 27 September 2016
Public product data sheet
COMPANY PUBLIC
1 General description
The P60D145 dual interface secure microcontroller is part of the most recent P60-
Step-Up! family generation and builds on the IntegralSecurity architecture. It delivers
unprecedented security, extended memory footprint, and highest performance across all
typical up-to-date requested fast transaction cases in Payment and eGov. Furthermore, it
comes with comprehensive options of ready-to-use MIFAREfunctionality and certified
crypto library modules and can be ordered in various advanced package options for
contact, dual interface, and contactless operation.
2 Features and benefits
2.1 Key features
User EEPROM: up to 142,5 KB
User ROM:
512 KB, y = P or M or D or J
586 KB, y = X
User RAM: up to 10176 Bytes
Dual Interface Type according to ISO/IEC 14443/7816
Rich option choice of certified convergence implementations:
y = P (Plain, no convergence implementations)
y = X (Plain, no convergence implementations, extended User ROM)
y = M (MIFARE Plus/Classic implementation)
y = D (MIFARE DESFire EV1 implementation)
y = J (Joint, common MIFARE Plus/Classic/DESFire EV1 implementation)
Contactless VHBR data rate up to 1.7 Mbit/s (card to reader)
Hardware-based Physically Unclonable Function (PUF) implemented: provides strong
protection for secret keys and data
SmartICE Development tool chain with true bond-out chip and Softmasking Device
allows faster time to market
2.2 Hardware features
Economic and resilient ROM/EEPROM design
data retention time: 25 years minimum
endurance: 500000 cycles
versatile EEPROM programming: 1 B to 256 B at a time
SmartMX2 CPU with orthogonal instruction set offering 32-/24-/16-/8-bit instructions
optimized for secured and low-power smart card applications




 P60D145_SDS
NXP Semiconductors
P60D145_SDS
SmartMX2 Family P60D145y
Dedicated high-performance secure coprocessor FAME2 for Public Key Infrastructure
(PKI) cryptography (RSA, ECC)
High-performance secured hardware support for symmetric block cipher algorithms:
Dual/triple DES and AES, all key lengths
Dedicated hardware support for SEED and OSCCA algorithms, multiple key and data
register sets for parallel data/key loading and calculation
True Random Number Generator (compliant to AIS-31)
16-bit and 32-bit CRC coprocessor supporting fast memory-verify functionality Memory
Management Unit (MMU):
16 segment cache entries and performance improvements
Supporting integral concept for secure code fetch and execution
Copy Machine offering data transfer between all Special Function Registers and all
Memory instances without CPU interaction
Watchdog Timer supporting secure code execution, Time Stamp Counter, Real Time
Clock
Continuous operation from 1.62 V up to 5.5 V
Operating ambient temperature from -25 °C to +85 °C
Selection of optimized antenna adaptations for respectively Class 1 ("ID1") and Class
2 ("1/2 ID1") antenna dimensions; additional option of common adaptation for both
Class1 and Class2
2.3 Security features
Outstanding Glue Logic chip layout based on the IntegralSecurityarchitecture
concept:
Most efficient and proven protection against reverse engineering
Impossible to recognize logical blocks by means of optical inspection
Advanced security sensors on clock, temperature, supply voltage, light, and single fault
injection
Active and dynamic shielding
Advanced memory security (encryption and physical measures) for RAM, EEPROM
and ROM
OS controlled access restriction mechanism to peripherals in user mode
Programmable card disable feature
Physically Unclonable Function hardware support to secure keys against new attack
scenarios
Metal layer design for highest attack resilience
No general standard core or re-used hard macro applied
No use of ROM-based micro code
Selection of optimized antenna adaptations for respectively Class 1 (ID1) and Class 2
(1/2 ID1) antenna dimensions, additional option of common adaptation for both Class1
and Class2
Certificates and approvals; Common Criteria up to EAL6+, EMVCo
One common certificate for controllers with or without MIFARE functionality offers high
re-use for any composite certification
P60D145_SDS
Public product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 27 September 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2/7




 P60D145_SDS
NXP Semiconductors
P60D145_SDS
SmartMX2 Family P60D145y
2.4 Additional features
CC security certified crypto library as a commercial option:
Consists of easy to use APIs for all algorithms, allows for dynamic use of memory
resources
Safeguards secure operation in both contact and contactless mode
Includes state-of-the-art and future-proof built-in security features to avoid power
(SPA/DPA), timing and fault attacks (DFA)
Every module is available separately
RSA encryption and decryption (256 … 4096 bit key length)
RSA signature generation and verification (256 … 4096 bit key length)
RSA key generation (plain and CRT format, 256 … 4096 bit key length)
ECC over GF(p) signature generation and verification (128 … 576 bit key length
ECC over GF(p) key generation and Diffie-Hellman key exchange (128 … 576 bit key
length)
ECC over GF(p) full point addition
SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hash computation
DES encryption, decryption and MAC (S-DES and T-DES with 2 & 3 keys)
AES encryption, decryption and MAC calculation (128, 192, 256 bit key length)
Pseudo Random number generation based on a deterministic random number
generator, generator of type K4
Rich set of MIFAREFlex configuration options available as selectable mix of card
data sizes:
MIFARE Classic/Plus (up to 4 KB)
MIFARE DESFire EV1 (up to 32 KB)
In-built functionality, no additional User ROM area needed
Service on batch, wafer or die-individual security data, secure transport keys:
Various EEPROM initialization options available to facilitate customer’s
personalization
Comprehensive offer on NXP Trust Provisioning service options
3 Development tools
Development tool chain, based on approved suppliers Keil and Ashling:
Well-perceived μVision user interface
Fast and efficient compiler, loader and timing-accurate simulator software
High-performance emulation hardware “SmartICE series”
Close-to-product emulation safeguarded via a true bond-out controller
Dual Interface Softmask Device (SMD) P60D289 for fast Flash-based prototyping
Tutorial Libraries with dedicated customer application support via local NXP Field
Application Engineers
P60D145_SDS
Public product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 27 September 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3/7




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