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hex inverter. CD4069UBF Datasheet

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hex inverter. CD4069UBF Datasheet
















CD4069UBF inverter. Datasheet pdf. Equivalent













Part

CD4069UBF

Description

CMOS hex inverter



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity CD4069UB SCHS054E – NOVEMBER 1998 – REVISED JANUARY 2019 CD4069UB CMOS hex inverter 1 Features •1 Stan dardized symmetrical output characteris tics • Medium speed operation: tPHL, tPLH = 30 ns at 10 V (Typical) • 100% Tested for quiescent current at 20 V Maximum input current of 1 .
Manufacture

Texas Instruments

Datasheet
Download CD4069UBF Datasheet


Texas Instruments CD4069UBF

CD4069UBF; µA at 18 V over full package-temperatur e range, 100 nA at 18 V and 25°C • M eets all requirements of JEDEC tentativ e standard No. 13B, Standard Specificat ions for Description of B Series CMOS D evices 2 Applications • Logic inversi on • Pulse shaping • Oscillators High-input-impedance amplifiers 3 De scription The CD4069UB device consist o f six CMOS inverter circuits. .


Texas Instruments CD4069UBF

These devices are intended for all gener alpurpose inverter applications where t he mediumpower TTL-drive and logic-leve l-conversion capabilities of circuits s uch as the CD4009 and CD4049 hex invert er and buffers are not required. Devic e Information(1) PART NUMBER PACKAGE (PINS) BODY SIZE (NOM) CD4069UBE PDI P (14) 19.30 mm × 6.35 mm CD4069UBF CDIP (14) 19.56 m.


Texas Instruments CD4069UBF

m × 6.67 mm CD4069UBM SOIC (14) 8.65 mm × 3.91 mm CD4069UBNSR SO (14) 1 0.30 mm × 5.30 mm CD4069UBPW TSSOP ( 14) 5.00 mm × 4.40 mm (1) For all av ailable packages, see the orderable add endum at the end of the data sheet. CD 4069UB Functional Diagram A 1 2 G=A B 3 4 H=B C 5 6 I=C D 9 8 J=D E 11 10 K = E F 13 VDD = Pin 14 VSS = Pin 7 12 L = F .





Part

CD4069UBF

Description

CMOS hex inverter



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity CD4069UB SCHS054E – NOVEMBER 1998 – REVISED JANUARY 2019 CD4069UB CMOS hex inverter 1 Features •1 Stan dardized symmetrical output characteris tics • Medium speed operation: tPHL, tPLH = 30 ns at 10 V (Typical) • 100% Tested for quiescent current at 20 V Maximum input current of 1 .
Manufacture

Texas Instruments

Datasheet
Download CD4069UBF Datasheet




 CD4069UBF
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
CD4069UB
SCHS054E – NOVEMBER 1998 – REVISED JANUARY 2019
CD4069UB CMOS hex inverter
1 Features
1 Standardized symmetrical output characteristics
• Medium speed operation: tPHL, tPLH = 30 ns at 10
V (Typical)
• 100% Tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full
package-temperature range, 100 nA at 18 V and
25°C
• Meets all requirements of JEDEC tentative
standard No. 13B, Standard Specifications for
Description of B Series CMOS Devices
2 Applications
• Logic inversion
• Pulse shaping
• Oscillators
• High-input-impedance amplifiers
3 Description
The CD4069UB device consist of six CMOS inverter
circuits. These devices are intended for all general-
purpose inverter applications where the medium-
power TTL-drive and logic-level-conversion
capabilities of circuits such as the CD4009 and
CD4049 hex inverter and buffers are not required.
Device Information(1)
PART NUMBER
PACKAGE
(PINS)
BODY SIZE (NOM)
CD4069UBE
PDIP (14)
19.30 mm × 6.35 mm
CD4069UBF
CDIP (14)
19.56 mm × 6.67 mm
CD4069UBM
SOIC (14)
8.65 mm × 3.91 mm
CD4069UBNSR
SO (14)
10.30 mm × 5.30 mm
CD4069UBPW
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
CD4069UB Functional Diagram
A
1
2
G=A
B
3
4
H=B
C
5
6
I=C
D
9
8
J=D
E 11
10 K = E
F 13
VDD = Pin 14
VSS = Pin 7
12 L = F
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




 CD4069UBF
CD4069UB
SCHS054E – NOVEMBER 1998 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 4
6.5 Electrical Characteristics – Dynamic......................... 5
6.6 Electrical Characteristics – Static.............................. 5
6.7 Typical Characteristics .............................................. 8
7 Parameter Measurement Information .................. 9
8 Detailed Description ............................................ 13
8.1 Overview ................................................................ 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description ................................................ 13
8.4 Device Functional Modes ....................................... 13
9 Application and Implementation ........................ 14
9.1 Application Information .......................................... 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................ 16
11.2 Layout Example ................................................... 16
12 Device and Documentation Support ................. 17
12.1 Device Support...................................................... 17
12.2 Documentation Support ........................................ 17
12.3 Community Resource............................................ 17
12.4 Trademarks ........................................................... 17
12.5 Electrostatic Discharge Caution ............................ 17
12.6 Glossary ................................................................ 17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2016) to Revision E
Page
• Removed artifact "–" at tPHLterm on the second Features bullet ........................................................................................... 1
• Corrected VI spec MIN/MAX values in the Abs Max Ratings table ....................................................................................... 4
• Corrected parameter IDD max term to IDD in the Elec Characteristics table ........................................................................... 5
• Corrected parameter IOL min term to IOL in the Elec Characteristics table ............................................................................ 5
• Corrected parameter VOL max term to VOL in the Elec Characteristics table ......................................................................... 6
• Corrected parameter VIL max term to VIL in the Elec Characteristics table ........................................................................... 6
• Corrected parameter VIH min term to VIH in the Elec Characteristics table ........................................................................... 6
• Corrected parameter IIN max term to IIN in the Elec Characteristics table ............................................................................. 7
• Added Y-axis label to Figure 1 image object ......................................................................................................................... 8
• Changed text string from " –tPHL" to "of tPHL" in the Feature Description paragraph. ........................................................... 13
Changes from Revision C (August 2003) to Revision D
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
2
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Product Folder Links: CD4069UB
Copyright © 1998–2019, Texas Instruments Incorporated




 CD4069UBF
www.ti.com
5 Pin Configuration and Functions
CD4069UB
SCHS054E – NOVEMBER 1998 – REVISED JANUARY 2019
D, J, N, NS, and PW Packages
14-Pin PDIP, CDIP, SOIC, SO, and TSSOP
Top View
A
1
G=A
2
B
3
H=B
4
C
5
I=C
6
VSS
7
14
VDD
13
F
12
L=F
11
E
10
K=E
9
D
8
J=D
NAME
A
B
C
D
E
F
G=A
H=B
I=C
J=D
K=E
L=F
VDD
VSS
PIN
NO.
1
3
5
9
11
13
2
4
6
8
10
12
14
7
Pin Functions
I/O
DESCRIPTION
I
A input
I
B input
I
C input
I
D input
I
E input
I
F input
O
G output
O
H output
O
I output
O
J output
O
K output
O
L output
Positive supply
Negative supply
Copyright © 1998–2019, Texas Instruments Incorporated
Product Folder Links: CD4069UB
Submit Documentation Feedback
3




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