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N-Channel MOSFET. 75333S Datasheet

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N-Channel MOSFET. 75333S Datasheet






75333S MOSFET. Datasheet pdf. Equivalent




75333S MOSFET. Datasheet pdf. Equivalent





Part

75333S

Description

N-Channel MOSFET



Feature


HUF75333G3, HUF75333P3, HUF75333S3S, HUF 75333S3 Data Sheet December 2001 66A , 55V, 0.016 Ohm. N-Channel UltraFET Po wer MOSFETs These N-Channel power MOSFE Ts are manufactured using the innovativ e UltraFET® process. This advanced pro cess technology achieves the lowest pos sible on-resistance per silicon area, r esulting in outstanding performance. Th is device is capabl.
Manufacture

Fairchild Semiconductor

Datasheet
Download 75333S Datasheet


Fairchild Semiconductor 75333S

75333S; e of withstanding high energy in the ava lanche mode and the diode exhibits very low reverse recovery time and stored c harge. It was designed for use in appli cations where power efficiency is impor tant, such as switching regulators, swi tching convertors, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and batter y-operated product.


Fairchild Semiconductor 75333S

s. . Ordering Information PART NUMBER PACKAGE BRAND HUF75333G3 TO-247 75 333G HUF75333P3 TO-220AB 75333P HUF 75333S3S TO-263AB 75333S HUF75333S3 TO-262AA 75333S NOTE: When ordering, use the entire part number. Add the su ffix T to obtain the TO-263AB variant i n tape and reel, e.g., HUF75333S3ST. P ackaging JEDEC STYLE TO-247 SOURCE DRA IN GATE Features .


Fairchild Semiconductor 75333S

• 66A, 55V • Simulation Models - Tem perature Compensated PSPICE® and SABER ™ Models - SPICE and SABER Thermal Im pedance Models Available on the WEB at: www.fairchildsemi.com • Peak Current vs Pulse Width Curve • UIS Rating Cu rve • Related Literature - TB334, “ Guidelines for Soldering Surface Mount Components to PC Boards” Formerly dev elopmental type TA75333 Symbol D G .

Part

75333S

Description

N-Channel MOSFET



Feature


HUF75333G3, HUF75333P3, HUF75333S3S, HUF 75333S3 Data Sheet December 2001 66A , 55V, 0.016 Ohm. N-Channel UltraFET Po wer MOSFETs These N-Channel power MOSFE Ts are manufactured using the innovativ e UltraFET® process. This advanced pro cess technology achieves the lowest pos sible on-resistance per silicon area, r esulting in outstanding performance. Th is device is capabl.
Manufacture

Fairchild Semiconductor

Datasheet
Download 75333S Datasheet




 75333S
HUF75333G3, HUF75333P3, HUF75333S3S,
HUF75333S3
Data Sheet
December 2001
66A, 55V, 0.016 Ohm. N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching convertors, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products. .
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75333G3
TO-247
75333G
HUF75333P3
TO-220AB
75333P
HUF75333S3S
TO-263AB
75333S
HUF75333S3
TO-262AA
75333S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75333S3ST.
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
Features
• 66A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA75333
Symbol
D
G
S
JEDEC TO-220AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(TAB)
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
JEDEC TO-262ABA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2003 Fairchild Semiconductor Corporation
HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1




 75333S
HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . .
Derate Above 25oC
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PD
...
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg
55
55
±20
66
Figure 4
Figures 6, 14, 15
150
1
-55 to 175
300
260
UNITS
V
V
V
A
W
W/oC
oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
VDS = 50V, VGS = 0V
VDS = 45V, VGS = 0V, TC = 150oC
VGS = ±20V
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
VGS(TH)
rDS(ON)
VGS = VDS, ID = 250µA (Figure 10)
ID = 66A, VGS = 10V (Figure 9)
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
RθJC
RθJA
(Figure 3)
TO-247
TO-220, TO-263
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
Turn-Off Time
tOFF
GATE CHARGE SPECIFICATIONS
VDD = 30V, ID 66A,
RL = 0.455, VGS = 10V,
RGS = 6.8
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Qg(TOT)
Qg(10)
Qg(TH)
Qgs
Qgd
VGS = 0V to 20V
VGS = 0V to 10V
VGS = 0V to 2V
VDD = 30V,
ID 66A,
RL = 0.455
Ig(REF) = 1.0mA
(Figure 13)
MIN TYP MAX UNITS
55
-
-
V
-
-
1
µA
-
-
250
µA
-
-
±100
nA
2
-
4
V
-
0.013 0.016
-
-
1
oC/W
-
-
30
oC/W
-
-
62
oC/W
-
-
100
ns
-
12
-
ns
-
55
-
ns
-
11
-
ns
-
25
-
ns
-
-
55
ns
-
70
85
nC
-
40
50
nC
-
2.5
3.0
nC
-
6.2
-
nC
-
16
-
nC
©2003 Fairchild Semiconductor Corporation
HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1




 75333S
HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
TEST CONDITIONS
VSD
trr
QRR
ISD = 66A
ISD = 66A, dISD/dt = 100A/µs
ISD = 66A, dISD/dt = 100A/µs
Typical Performance Curves
MIN TYP MAX UNITS
-
1300
-
pF
-
480
-
pF
-
115
-
pF
MIN
TYP
MAX UNITS
-
-
1.25
V
-
-
75
ns
-
-
140
nC
1.2
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125 150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
70
60
50
40
30
20
10
0
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
0.01
10-5
SINGLE PULSE
10-4
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2003 Fairchild Semiconductor Corporation
HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1



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