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N-Channel MOSFET. 75329G Datasheet

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N-Channel MOSFET. 75329G Datasheet






75329G MOSFET. Datasheet pdf. Equivalent




75329G MOSFET. Datasheet pdf. Equivalent





Part

75329G

Description

N-Channel MOSFET



Feature


HUF75329G3, HUF75329P3, HUF75329S3S Dat a Sheet December 2001 49A, 55V, 0.024 Ohm, N-Channel UltraFET Power MOSFETs These N-Channel power MOSFETs are manuf actured using the innovative UltraFET® process. This advanced process technol ogy achieves the lowest possible on-res istance per silicon area, resulting in outstanding performance. This device is capable of withsta.
Manufacture

Fairchild Semiconductor

Datasheet
Download 75329G Datasheet


Fairchild Semiconductor 75329G

75329G; nding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It wa s designed for use in applications wher e power efficiency is important, such a s switching regulators, switching conve rters, motor drivers, relay drivers, lo wvoltage bus switches, and power manage ment in portable and battery-operated p roducts. Formerly .


Fairchild Semiconductor 75329G

developmental type TA75329. Ordering In formation PART NUMBER PACKAGE BRAND HUF75329G3 TO-247 75329G HUF75329P3 TO-220AB 75329P HUF75329S3S TO-263 AB 75329S NOTE: When ordering, use th e entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75329S3ST. Packagin g JEDEC STYLE TO-247 SOURCE DRAIN GAT E Features • 49A,.


Fairchild Semiconductor 75329G

55V • Ultra Low On-Resistance, rDS(ON ) = 0.024Ω • Temperature Compensati ng PSPICE® and SABER™ Models - Avail able on the web at: www.fairchildsemi.c om • Thermal Impedance PSPICE and SAB ER Models • Peak Current vs Pulse Wid th Curve • UIS Rating Curve • Relat ed Literature - TB334, “Guidelines fo r Soldering Surface Mount Components to PC Boards” Symbol D G S JEDEC TO-22.

Part

75329G

Description

N-Channel MOSFET



Feature


HUF75329G3, HUF75329P3, HUF75329S3S Dat a Sheet December 2001 49A, 55V, 0.024 Ohm, N-Channel UltraFET Power MOSFETs These N-Channel power MOSFETs are manuf actured using the innovative UltraFET® process. This advanced process technol ogy achieves the lowest possible on-res istance per silicon area, resulting in outstanding performance. This device is capable of withsta.
Manufacture

Fairchild Semiconductor

Datasheet
Download 75329G Datasheet




 75329G
HUF75329G3, HUF75329P3, HUF75329S3S
Data Sheet
December 2001
49A, 55V, 0.024 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75329.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75329G3
TO-247
75329G
HUF75329P3
TO-220AB
75329P
HUF75329S3S
TO-263AB
75329S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75329S3ST.
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
Features
• 49A, 55V
Ultra Low On-Resistance, rDS(ON) = 0.024
• Temperature Compensating PSPICE® and SABER™
Models
- Available on the web at: www.fairchildsemi.com
• Thermal Impedance PSPICE and SABER Models
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-220AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(TAB)
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75329G3, HUF75329P3, HUF75329S3S Rev. B




 75329G
HUF75329G3, HUF75329P3, HUF75329S3SOGM
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
55
V
55
V
±20
V
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . .
Derate Above 25oC
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PD
...
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg
49
Figure 4
Figures 6, 14, 15
128
0.86
-55 to 175
300
260
A
W
W/oC
oC
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
VDS = 50V, VGS = 0V
VDS = 45V, VGS = 0V, TC = 150oC
VGS = ±20V
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
VGS(TH)
rDS(ON)
VGS = VDS, ID = 250µA (Figure 10)
ID = 49A, VGS = 10V (Figure 9)
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
RθJC
RθJA
(Figure 3)
TO-247
TO-220, TO-263
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
tON
td(ON)
tr
td(OFF)
tf
tOFF
VDD = 30V, ID 49A,
RL = 0.61, VGS = 10V,
RGS = 9.1
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Qg(TOT)
Qg(10)
Qg(TH)
Qgs
Qgd
VGS = 0V to 20V
VGS = 0V to 10V
VGS = 0V to 2V
VDD = 30V,
ID 49A,
RL = 0.61
Ig(REF) = 1.0mA
(Figure 13)
MIN TYP MAX UNITS
55
-
-
V
-
-
1
µA
-
-
250
µA
-
-
±100
nA
2
-
4
V
-
0.020 0.024
-
-
1.17 oC/W
-
-
30
oC/W
-
-
62
oC/W
-
-
105
ns
-
12
-
ns
-
58
-
ns
-
33
-
ns
-
33
-
ns
-
-
100
ns
-
60
75
nC
-
35
43
nC
-
2.0
2.5
nC
-
5
-
nC
-
13
-
nC
©2001 Fairchild Semiconductor Corporation
HUF75329G3, HUF75329P3, HUF75329S3S Rev. B




 75329G
HUF75329G3, HUF75329P3, HUF75329S3S
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
VSD
trr
QRR
TEST CONDITIONS
ISD = 49A
ISD = 49A, dISD/dt = 100A/µs
ISD = 49A, dISD/dt = 100A/µs
Typical Performance Curves
MIN TYP MAX UNITS
-
1060
-
pF
-
405
-
pF
-
95
-
pF
MIN
TYP
MAX UNITS
-
-
1.25
V
-
-
72
ns
-
-
120
nC
1.2
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125 150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
60
50
40
30
20
10
0
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.0110-5
SINGLE PULSE
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
HUF75329G3, HUF75329P3, HUF75329S3S Rev. B



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