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PHASE-LOCKED LOOP. TLC2933 Datasheet

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PHASE-LOCKED LOOP. TLC2933 Datasheet






TLC2933 LOOP. Datasheet pdf. Equivalent




TLC2933 LOOP. Datasheet pdf. Equivalent





Part

TLC2933

Description

HIGH-PERFORMANCE PHASE-LOCKED LOOP



Feature


TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LO OP D Voltage-Controlled Oscillator (VC O) Section: – Ring Oscillator Using O nly One External Bias Resistor (RBIAS) – Lock Frequency: 43 MHz to 100 MHz ( VDD = 5 V ±5%, TA = – 20°C to 75°C , ×1 Output) 37 MHz to 55 MHz (VDD = 3 V ±5%, TA = – 20°C to 75°C) D Pha se-Frequency Detector (PFD) Section Inc ludes a High-Speed Edge-Triggered.
Manufacture

Texas Instruments

Datasheet
Download TLC2933 Datasheet


Texas Instruments TLC2933

TLC2933; Detector With Internal Charge Pump D In dependent VCO, PFD Power-Down Mode D Th in Small-Outline Package (14 terminal) D CMOS Technology D Typical Application s: – Frequency Synthesis – Modulati on/Demodulation – Fractional Frequenc y Division D CMOS Input Logic Level SL AS136A – APRIL 1996 – REVISED JUNE 1997 PW PACKAGE† (TOP VIEW) LOGIC V DD 1 TEST 2 VCO OUT 3 FI.


Texas Instruments TLC2933

N – A 4 FIN – B 5 PFD OUT 6 LO GIC GND 7 14 VCO VDD 13 BIAS 12 VCO IN 11 VCO GND 10 VCO INHIBIT 9 PFD INHIBIT 8 NC † Available in tape and reel only and ordered as the T LC2933PWLE. NC – No internal connecti on description The TLC2933 is designed for phase-locked-loop (PLL) systems an d is composed of a voltage-controlled o scillator (VCO) and an edg.


Texas Instruments TLC2933

e-triggered-type phase frequency detecto r (PFD). The oscillation frequency rang e of the VCO is set by an external bias resistor (RBIAS). The high-speed PFD w ith internal charge pump detects the ph ase difference between the reference fr equency input and signal frequency inpu t from the external counter. Both the V CO and the PFD have inhibit functions t hat can be used as.

Part

TLC2933

Description

HIGH-PERFORMANCE PHASE-LOCKED LOOP



Feature


TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LO OP D Voltage-Controlled Oscillator (VC O) Section: – Ring Oscillator Using O nly One External Bias Resistor (RBIAS) – Lock Frequency: 43 MHz to 100 MHz ( VDD = 5 V ±5%, TA = – 20°C to 75°C , ×1 Output) 37 MHz to 55 MHz (VDD = 3 V ±5%, TA = – 20°C to 75°C) D Pha se-Frequency Detector (PFD) Section Inc ludes a High-Speed Edge-Triggered.
Manufacture

Texas Instruments

Datasheet
Download TLC2933 Datasheet




 TLC2933
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
D Voltage-Controlled Oscillator (VCO)
Section:
– Ring Oscillator Using Only One
External Bias Resistor (RBIAS)
– Lock Frequency:
43 MHz to 100 MHz (VDD = 5 V ±5%,
TA = – 20°C to 75°C, ×1 Output)
37 MHz to 55 MHz (VDD = 3 V ±5%,
TA = – 20°C to 75°C)
D Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump
D Independent VCO, PFD Power-Down Mode
D Thin Small-Outline Package (14 terminal)
D CMOS Technology
D Typical Applications:
– Frequency Synthesis
– Modulation/Demodulation
– Fractional Frequency Division
D CMOS Input Logic Level
SLAS136A – APRIL 1996 – REVISED JUNE 1997
PW PACKAGE†
(TOP VIEW)
LOGIC VDD
1
TEST
2
VCO OUT
3
FIN – A
4
FIN – B
5
PFD OUT
6
LOGIC GND
7
14
VCO VDD
13
BIAS
12
VCO IN
11
VCO GND
10
VCO INHIBIT
9
PFD INHIBIT
8
NC
Available in tape and reel only and ordered as the
TLC2933PWLE.
NC – No internal connection
description
The TLC2933 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (RBIAS). The high-speed PFD with internal charge pump detects
the phase difference between the reference frequency input and signal frequency input from the external
counter. Both the VCO and the PFD have inhibit functions that can be used as a power-down mode. With the
high-speed and stable VCO characteristics, the TLC2933 is well suited for use in high-performance PLL
systems.
functional block diagram
FIN –A
FIN –B
PFD INHIBIT
4 Phase
5 Frequency 6
9 Detector
VCO IN
BIAS
PFD OUT VCO INHIBIT
TEST
12
13
10
Voltage-
Controlled
3
2 Oscillator
VCO OUT
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(PW)
– 20°C to 75°C TLC2933PWLE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1997, Texas Instruments Incorporated
1




 TLC2933
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
Terminal Functions
TERMINAL
NAME
NO.
BIAS
13
FIN – A
4
FIN – B
5
LOGIC GND
7
LOGIC VDD
1
NC
8
PFD INHIBIT
9
PFD OUT
6
TEST
2
VCO GND
11
VCO IN
12
VCO INHIBIT
10
VCO OUT
3
VCO VDD
14
I/O
DESCRIPTION
I Bias supply. An external resistor (RBIAS) between VCO VDD and BIAS supplies bias for adjusting the
oscillation frequency range.
I Input reference frequency f(REF IN) is applied to FIN – A.
I Input for VCO external counter output frequency f(FIN – B). FIN – B is nominally provided from the external
counter.
Ground for the internal logic.
Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce
cross-coupling between supplies.
No internal connection.
I PFD inhibit control. When PFD INHIBIT is high, PFD OUT is in the high-impedance state, see Table 2.
O PFD output. When the PFD INHIBIT is high, PFD OUT is in the high-impedance state.
I Test terminal. TEST connects to ground for normal operation.
Ground for VCO.
I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 1).
O VCO output. When VCO INHIBIT is high, VCO OUT is low.
Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling
between supplies.
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external resistor (RBIAS) connected between the VCO VDD
and the BIAS terminals. The oscillation frequency and range depends on this resistor value. While all resistor
values within the specified range result in excellent low temperature coefficients, the bias resistor value for the
minimum temperature coefficient is nominally 2.2 kwith 3-V VDD and nominally 2.4 kwith 5-V VDD. For the
lock frequency range refer to the recommended operating conditions. Figure 1 shows the typical frequency
variation and VCO control voltage.
VCO Oscillation Frequency Range
Bias Resistor (RBIAS)
1/2 VDD
VCO Control Voltage (VCO IN)
Figure 1. VCO Oscillation Frequency
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TLC2933
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode as shown in Table 1.
Table 1. VCO Inhibit Function
VCO INHIBIT
Low
High
VCO OSCILLATOR
Active
Stopped
VCO OUT
Active
Low level
IDD(VCO)
Normal
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B. For clock
recovery PLL systems, other types of phase detectors should be used.
FIN– A
FIN– B
PFD OUT
VOH
Hi-Z
VOL
Figure 2. PFD Function Timing Chart
PFD inhibit control
A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops
phase detection as shown in Table 2. A high level on the PFD INHIBIT terminal can also be used as the
power-down mode for the PFD.
Table 2. VCO Output Control Function
PFD INHIBIT
Low
High
DETECTION
Active
Stopped
PFD OUT
Active
Hi-Z
IDD(PFD)
Normal
Power Down
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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