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BUILDING BLOCK. TLC2943 Datasheet

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BUILDING BLOCK. TLC2943 Datasheet






TLC2943 BLOCK. Datasheet pdf. Equivalent




TLC2943 BLOCK. Datasheet pdf. Equivalent





Part

TLC2943

Description

HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK



Feature


TLC2943 HIGH-PERFORMANCE DUAL PHASE-LOCK ED BUILDING BLOCK SLAS249 – NOVEMBER 1999 D Dual TLC2933 by Multichip Modu le (MCM) Technology D Voltage-Controlle d Oscillators (VCO) Section – Complet e Oscillator Using Only One External Bi as Resistor (RBIAS) – Recommended Loc k Frequency Range – 37 MHz to 60 MHz (VDD = 3.3 V ± 0.15 V, TA = –20°C t o 75°C) – 43 MHz to 100 MHz (V.
Manufacture

Texas Instruments

Datasheet
Download TLC2943 Datasheet


Texas Instruments TLC2943

TLC2943; DD = 5 V ± 0.25 V, TA = –20°C to 75 C) D Includes a High Speed Edge-Trigge red Phase Frequency Detector (PFD) With Internal Charge Pump D Independent VCO , PFD Power-Down Mode description DB P ACKAGE (TOP VIEW) LOGIC_1 VDD 1 TEST_1 2 VCO_1 OUT 3 FIN-A_1 4 FIN-B_1 5 PFD_ 1 OUT 6 LOGIC_1 GND 7 GND 8 NC 9 NC 10 NC 11 GND 12 LOGIC_2 VDD 13 TEST_2 14 V CO_2 OUT 15 FIN-A_2 16 .


Texas Instruments TLC2943

FIN-B_2 17 PFD_2 OUT 18 LOGIC_2 GND 19 38 VCO_1 VDD 37 RBIAS _1 36 VCOIN_1 35 VCO_1 GND 34 VCO_1 INHIBIT 33 PFD_1 INH IBIT 32 NC 31 GND 30 NC 29 NC 28 NC 27 GND 26 VCO_2 VDD 25 RBIAS _2 24 VCOIN_2 23 VCO_2 GND 22 VCO_2 INHIBIT 21 PFD_2 INHIBIT 20 NC The TLC2943 is a multic hip module product that uses two TLC29 33 chips. The TLC2933 chip is composed of a voltage-cont.


Texas Instruments TLC2943

rolled oscillator (VCO) and an edge-trig gered-type phase frequency detector (P FD). The oscillation frequency range of the VCO is set by an external bias res istor (R BIAS ). The high-speed PFD wit h internal charge pump detects the phas e difference between the reference freq uency input and signal frequency input from the external counter. Both the VCO and the PFD have .

Part

TLC2943

Description

HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK



Feature


TLC2943 HIGH-PERFORMANCE DUAL PHASE-LOCK ED BUILDING BLOCK SLAS249 – NOVEMBER 1999 D Dual TLC2933 by Multichip Modu le (MCM) Technology D Voltage-Controlle d Oscillators (VCO) Section – Complet e Oscillator Using Only One External Bi as Resistor (RBIAS) – Recommended Loc k Frequency Range – 37 MHz to 60 MHz (VDD = 3.3 V ± 0.15 V, TA = –20°C t o 75°C) – 43 MHz to 100 MHz (V.
Manufacture

Texas Instruments

Datasheet
Download TLC2943 Datasheet




 TLC2943
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
D Dual TLC2933 by Multichip Module
(MCM) Technology
D Voltage-Controlled Oscillators (VCO)
Section
Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
Recommended Lock Frequency
Range
37 MHz to 60 MHz
(VDD = 3.3 V ± 0.15 V, TA = –20°C
to 75°C)
43 MHz to 100 MHz
(VDD = 5 V ± 0.25 V, TA = –20°C
to 75°C)
D Includes a High Speed Edge-Triggered
Phase Frequency Detector (PFD) With
Internal Charge Pump
D Independent VCO, PFD Power-Down
Mode
description
DB PACKAGE
(TOP VIEW)
LOGIC_1 VDD 1
TEST_1 2
VCO_1 OUT 3
FIN-A_1 4
FIN-B_1 5
PFD_1 OUT 6
LOGIC_1 GND 7
GND 8
NC 9
NC 10
NC 11
GND 12
LOGIC_2 VDD 13
TEST_2 14
VCO_2 OUT 15
FIN-A_2 16
FIN-B_2 17
PFD_2 OUT 18
LOGIC_2 GND 19
38 VCO_1 VDD
37 RBIAS _1
36 VCOIN_1
35 VCO_1 GND
34 VCO_1 INHIBIT
33 PFD_1 INHIBIT
32 NC
31 GND
30 NC
29 NC
28 NC
27 GND
26 VCO_2 VDD
25 RBIAS _2
24 VCOIN_2
23 VCO_2 GND
22 VCO_2 INHIBIT
21 PFD_2 INHIBIT
20 NC
The TLC2943 is a multichip module product that
uses two TLC2933 chips. The TLC2933 chip is
composed of a voltage-controlled oscillator (VCO) and an edge-triggered-type phase frequency detector
(PFD). The oscillation frequency range of the VCO is set by an external bias resistor (R BIAS ). The high-speed
PFD with internal charge pump detects the phase difference between the reference frequency input and signal
frequency input from the external counter. Both the VCO and the PFD have inhibit functions that can be used
as a power-down mode. The high-speed and stable VCO characteristics of the TLC2933 make the TLC2943
suitable for use in dual high-performance phase-locked loop (PLL) systems.
TA
– 20°C to 75°C
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE (DB)
TLC2943IDB
TLC2943IDBR (Tape and Reel)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
1




 TLC2943
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
functional block diagram
VCO_1 OUT
VCO_1 INHIBIT
VCO_2 OUT
VCO_2 INHIBIT
VCOIN_1
FIN-A_1
FIN-B_1
VCO_1
PFD_1
VCO_2
PFD_2
VCOIN_2
FIN-A_2
FIN-B_2
PFD_1 INHIBIT
PFD_1 OUT
PFD_2 INHIBIT
PFD_2 OUT
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TLC2943
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
TERMINAL
NAME
NO.
GND
8, 31
12, 27
FIN–A_1,
4
FIN–B_1
5
FIN–A_2,
16
FIN–B_2
17
LOGIC_1 GND
7
LOGIC_2 GND
19
LOGIC_1 VDD
1
LOGIC_2 VDD
NC
13
9, 10,
11, 20,
28, 29,
30, 32
PFD_1 INHIBIT 33
PFD_2 INHIBIT 21
PFD_1 OUT
6
PFD_2 OUT
18
RBIAS_1
37
RBIAS_2
25
TEST_1
2
TEST_2
14
VCO_1 GND
35
VCO_2 GND
23
VCO_1 INHIBIT 34
VCO_2 INHIBIT 22
VCO_1 OUT
3
VCO_2 OUT
15
VCO_1 VDD
38
VCO_2 VDD
26
VCOIN_1
36
VCOIN_2
24
Terminal Functions
SLAS249 – NOVEMBER 1999
I/O
DESCRIPTION
Common GND for chip 1
Common GND for chip 2
Reference frequency signal input and comparison frequency signal input for PFD_1. fREF–IN_1 inputs
I to FIN-A_1, and comparison frequency input from external counter logic to FIN–B_1, for a lag-lead filter
use as LPF.
Reference frequency signal input and comparison frequency signal input for PFD_2. fREF–IN_2 inputs
I to FIN-A_2, and comparison frequency input from external counter logic to FIN-B_2, for a lag-lead filter use
as LPF.
Ground for the internal logic of chip 1
Ground for the internal logic of chip 2
Power supply for the internal logic of chip 1. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.
Power supply for the internal logic of chip 2. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.
No internal connection
I
PFD inhibit control for chip 1. When PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state,
see Table 2.
I
PFD inhibit control for chip 2. When PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state,
see Table 2.
O PFD output of chip 1. When the PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state.
O PFD output of chip 2. When the PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state.
I
Bias supply for VCO_1. An external resistor (RBIAS) between VCO_1 VDD and BIAS_1 supplies bias for
adjusting the oscillation frequency range of VCO_1.
I
Bias supply for VCO_2. An external resistor (RBIAS) between VCO_2 VDD and BIAS_2 supplies bias for
adjusting the oscillation frequency range of VCO_2.
Test terminal. TEST connects to LOGIC_1 GND for normal operation.
Test terminal. TEST connects to LOGIC_2 GND for normal operation.
GND for VCO_1
GND for VCO_2
I VCO inhibit control for chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low (see Table 1).
I VCO inhibit control for chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low (see Table 1).
O VCO output of chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low.
O VCO output of chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low.
Power supply for VCO_1. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.
Power supply for VCO_2. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.
VCO_1 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
I oscillation frequency.
I
VCO_2 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3



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