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BCD Counter. CD4553 Datasheet

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BCD Counter. CD4553 Datasheet






CD4553 Counter. Datasheet pdf. Equivalent




CD4553 Counter. Datasheet pdf. Equivalent





Part

CD4553

Description

(MC14553B) 3 Digit BCD Counter



Feature


MC14553B 3-Digit BCD Counter The MC14553 B 3–digit BCD counter consists of 3 n egative edge triggered BCD counters tha t are cascaded synchronously. A quad la tch at the output of each counter permi ts storage of any given count. The info rmation is then time division multiplex ed, providing one BCD number or digit a t a time. Digit select outputs provide display control. All.
Manufacture

ON

Datasheet
Download CD4553 Datasheet


ON CD4553

CD4553; outputs are TTL compatible. An on–chi p oscillator provides the low–frequen cy scanning clock which drives the mult iplexer output selector. This device is used in instrumentation counters, cloc k displays, digital panel meters, and a s a building block for general logic ap plications. http://onsemi.com MARKING DIAGRAMS 16 PDIP–16 P SUFFIX CASE 64 8 MC14553BCP AWLYYWW 1 .


ON CD4553

• • • • • • • TTL Compati ble Outputs On–Chip Oscillator Cascad able Clock Disable Input Pulse Shaping Permits Very Slow Rise Times on Input C lock Output Latches Master Reset 16 SO IC–16 DW SUFFIX CASE 751G 1 14553B A WLYYWW MAXIMUM RATINGS (Voltages Refer enced to VSS) (Note 1.) Symbol VDD Vin, Vout Iin Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Out.


ON CD4553

put Voltage Range (DC or Transient) Inpu t Current (DC or Transient) per Pin Out put Current (DC or Transient) per Pin P ower Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temp erature Range Lead Temperature (8–Sec ond Soldering) Value –0.5 to +18.0 0.5 to VDD + 0.5 ±10 +20 500 –55 to +125 –65 to +150 260 Unit V V mA A W L, L YY, Y WW, W = Assembly L.

Part

CD4553

Description

(MC14553B) 3 Digit BCD Counter



Feature


MC14553B 3-Digit BCD Counter The MC14553 B 3–digit BCD counter consists of 3 n egative edge triggered BCD counters tha t are cascaded synchronously. A quad la tch at the output of each counter permi ts storage of any given count. The info rmation is then time division multiplex ed, providing one BCD number or digit a t a time. Digit select outputs provide display control. All.
Manufacture

ON

Datasheet
Download CD4553 Datasheet




 CD4553
MC14553B
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
–0.5 to +18.0
–0.5 to VDD + 0.5
Unit
V
V
Iin Input Current
(DC or Transient) per Pin
±10 mA
Iout Output Current
(DC or Transient) per Pin
+20 mA
PD Power Dissipation,
per Package (Note 2.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
–55 to +125
–65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14553BCP
AWLYYWW
1
16
SOIC–16
DW SUFFIX
CASE 751G
14553B
AWLYYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14553BCP
MC14553BDW
PDIP–16
SOIC–16
25/Rail
47/Rail
© Semiconductor Components Industries, LLC, 2001
February, 2001 – Rev. 5
1
Publication Order Number:
MC14553B/D




 CD4553
MC14553B
43
CIA CIB Q0
9
12 CLOCK
Q1 7
10 LE
Q2 6
Q3 5
11 DIS
O.F. 14
DS1 2
13 MR
DS2 1
DS3 15
VDD = PIN 16
VSS = PIN 8
Figure 1. Block Diagram
TRUTH TABLE
Inputs
Master
Reset
Clock Disable
LE
Outputs
0
00
No Change
0
00
Advance
0X1X
No Change
01
0 Advance
01
0 No Change
0 0XX
No Change
0 XX
Latched
0 XX 1
Latched
1 X X 0 Q0 = Q1 = Q2 = Q3 = 0
X = Don’t Care
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2




 CD4553
MC14553B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55_C
25_C
125_C
Characteristic
VDD Typ
Symbol Vdc Min Max Min (Note 3.) Max Min Max Unit
Output Voltage
Vin = VDD or 0
“0” Level VOL
5.0
10
15
— 0.05 —
— 0.05 —
— 0.05 —
0 0.05 — 0.05 Vdc
0 0.05 — 0.05
0 0.05 — 0.05
Vin = 0 or VDD
“1” Level VOH
5.0 4.95 — 4.95
10 9.95 — 9.95
15 14.95 — 14.95
5.0
10
15
— 4.95 — Vdc
— 9.95 —
— 14.95 —
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source —
Pin 3
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source —
Other
Outputs
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink —
Pin 3
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink — Other
Outputs
Input Current
Input Capacitance
(Vin = 0)
Quiescent Current
(Per Package)
MR = VDD
Total Supply Current (Note 4., 5.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
VIL
VIH
IOH
IOL
Iin
Cin
IDD
IT
Vdc
5.0 — 1.5 — 2.25 1.5 — 1.5
10 — 3.0 — 4.50 3.0 — 3.0
15 — 4.0 — 6.75 4.0 — 4.0
5.0 3.5 — 3.5 2.75
10 7.0 — 7.0 5.50
15 11 — 11 8.25
Vdc
— 3.5 —
— 7.0 —
— 11 —
5.0 – 0.25
10 – 0.62
15 – 1.8
– 0.2
– 0.5
– 1.5
– 0.36
– 0.9
– 3.5
mAdc
— –0.14 —
— –0.35 —
— –1.1 —
5.0 – 0.64 — – 0.51 – 0.88
10 – 1.6 — – 1.3 – 2.25
15 – 4.2 — – 3.4 – 8.8
— – 0.36 — mAdc
— – 0.9 —
— – 2.4 —
5.0 0.5 — 0.4 0.88
10 1.1 — 0.9 2.25
15 1.8 — 1.5
8.8
— 0.28 — mAdc
— 0.65 —
— 1.20 —
5.0 3.0 — 2.5
10 6.0 — 5.0
15 18 — 15
4.0
8.0
20
— 1.6 — mAdc
— 3.5 —
— 10 —
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
————
5.0
7.5 —
— pF
5.0
5.0
0.010
5.0
150 µAdc
10 — 10 — 0.020 10 — 300
15 — 20 — 0.030 20 — 600
5.0
IT = (0.35 µA/kHz) f + IDD
µAdc
10 IT = (0.85 µA/kHz) f + IDD
15 IT = (1.50 µA/kHz) f + IDD
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
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3






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